IP Library › Granted Patent US 12,300,622
Granted Patent B2
US 12,300,622 · App. 18/460,481 · Granted May 13, 2025

Device packages including redistribution layers with carbon-based conductive elements, and methods of fabrication

Inventor: Eiichi Nakano (Boise, ID)
H01L23/5384H01L23/53233H01L23/53261H01L23/53276H01L23/5385H01L23/5386H01L25/117
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,300,622
App. No.
18/460,481
Granted
May 13, 2025
Kind
B2
Abstract

Semiconductor device packages include a redistribution layer (RDL) with carbon-based conductive elements. The carbon-based material of the RDL may have low electrical resistivity and may be thin (e.g., less than about 0.2 μm). Adjacent passivation material may also be thin (e.g., less than about 0.2 μm). Methods for forming the semiconductor device packages include forming the carbon-based material (e.g., at high temperatures (e.g., at least about 550° C.)) on an initial support wafer with a sacrificial substrate. Later or separately, components of a device region of the package may be formed and then joined to the initial support wafer before the sacrificial substrate is removed to leave the carbon-based material joined to the device region.

Claims (50)

1. A method for fabricating a semiconductor device package, the method comprising:

forming an initial support wafer comprising a redistribution layer on a sacrificial substrate, the redistribution layer comprising conductive elements comprising a conductive carbon-based material in a passivation material;

bonding the initial support wafer to an additional wafer to form a bonded structure, the additional wafer comprising a device region comprising circuitry comprising semiconductor device components, the device region also comprising vias extending through the circuitry;

after the bonding, inverting the bonded structure and removing the sacrificial substrate to leave the conductive carbon-based material over the additional wafer; and

forming openings extending through the passivation material to the conductive elements, the method forming a semiconductor device package comprising:

the redistribution layer comprising the conductive elements comprising the conductive carbon-based material, the conductive carbon-based material defining a vertical height, between a lower surface and an upper surface of the conductive carbon-based material, of less than about 0.2 μm;

the passivation material laterally between and partially overlapping the upper surface of the conductive elements, the passivation material defining the openings, the openings extending through the passivation material to the conductive elements; and

the device region directly adjacent the conductive carbon-based material of the conductive elements of the redistribution layer, wherein the device region further comprises the vias extending from the lower surface of the conductive carbon-based material and through the circuitry of the device region.

2. The method of claim 1 , wherein forming the initial support wafer comprises forming the redistribution layer so that the conductive carbon-based material and the passivation material each define a height of less than about 0.2 μm.

3. The method of claim 1 , wherein forming the initial support wafer comprises:

forming a sacrificial base material directly on the sacrificial substrate, the sacrificial base material comprising some of the passivation material;

forming a seed material directly on the sacrificial base material; and

forming the conductive carbon-based material directly on the seed material.

4. The method of claim 3 , further comprising, after removing the sacrificial substrate, removing the seed material.

5. The method of claim 3 , further comprising, patterning the conductive carbon-based material to define the conductive elements as discrete structures.

6. The method of claim 3 , wherein forming the initial support wafer further comprises:

patterning the conductive carbon-based material and the seed material to define the conductive elements as discrete structures spaced by additional openings; and

forming more of the passivation material in the additional openings.

7. The method of claim 1 , wherein forming the initial support wafer comprising the redistribution layer comprises:

forming the passivation material on the sacrificial substrate;

forming the conductive carbon-based material on the passivation material;

patterning the conductive carbon-based material to form the conductive elements as discrete structures defining additional openings between the discrete structures; and

filling the additional openings with an additional amount of the passivation material.

8. The method of claim 7 , wherein patterning the conductive carbon-based material precedes inverting the bonded structure.

9. The method of claim 1 , wherein forming the initial support wafer comprising the redistribution layer comprises:

forming the passivation material on the sacrificial substrate;

patterning the passivation material to define other openings; and

forming the conductive carbon-based material in the other openings defined in the passivation material to form the conductive elements comprising the conductive carbon-based material in the passivation material.

10. The method of claim 9 , further comprising, after removing the sacrificial substrate, forming more of the passivation material over the conductive carbon-based material.

11. A method for fabricating a semiconductor device package, the method comprising:

forming an initial support wafer comprising:

forming a conductive carbon-based material in a passivation material on a sacrificial substrate;

bonding a surface of the initial support wafer to another wafer comprising a device region comprising circuitry comprising semiconductor device components, the device region also comprising vias extending through the circuitry;

removing the sacrificial substrate; and

forming openings extending through the passivation material to the conductive carbon-based material,

the method forming a semiconductor device package comprising:

a redistribution layer comprising conductive elements comprising the conductive carbon-based material, the conductive carbon-based material defining a vertical height, between a lower surface and an upper surface of the conductive carbon-based material, of less than about 0.2 μm;

the passivation material laterally between and partially overlapping the upper surface of the conductive elements, the passivation material defining the openings, the openings extending through the passivation material to the conductive elements; and

the device region directly adjacent the conductive carbon-based material of the conductive elements of the redistribution layer, wherein the device region further comprises the vias extending from the lower surface of the conductive carbon-based material and through the circuitry of the device region.

12. The method of claim 11 , wherein forming the conductive carbon-based material in the passivation material on the sacrificial substrate comprises forming graphene in a dielectric material on a semiconductor substrate.

13. The method of claim 11 , wherein forming the conductive carbon-based material comprises forming the conductive carbon-based material at a temperature of at least 550° C. without exposing the other wafer comprising the semiconductor device components to the temperatures.

14. A device package, comprising:

a redistribution layer comprising conductive elements comprising a conductive carbon-based material defining a vertical height, between a lower surface and an upper surface of the conductive carbon-based material, of less than about 0.2 μm;

passivation material laterally between and partially overlapping the upper surface of the conductive elements, the passivation material defining openings extending therethrough to the conductive elements; and

a device region directly adjacent the conductive carbon-based material of the conductive elements of the redistribution layer, wherein the device region further comprises vias extending from the lower surface of the conductive carbon-based material and through circuitry of the device region.

15. The device package of claim 14 , wherein the conductive elements further comprise a seed material on the upper surface of the conductive carbon-based material.

16. The device package of claim 15 , wherein the openings defined by the passivation material extend directly to the seed material of the conductive elements.

17. The device package of claim 15 , wherein the seed material is not horizontally adjacent sidewalls of the conductive carbon-based material.

18. The device package of claim 14 , wherein the passivation material is directly laterally adjacent the conductive carbon-based material of the conductive elements.

19. The device package of claim 14 , wherein the conductive carbon-based material consists essentially of graphene.

Continuity (3)
Division 17076602 · Oct 21, 2020
Division 16236681 · Dec 31, 2018
Related Publication 20230411299A1 · Dec 21, 2023
References Cited (53)
US 7105930B2 · Lua et al. · 2006 [cited by applicant]
US 7326633B2 · Chen · 2008 [cited by applicant]
US 7470416B2 · Ishida · 2008 [cited by applicant]
US 8097947B2 · Lua et al. · 2012 [cited by applicant]
US 8178201B2 · Lee et al. · 2012 [cited by applicant]
US 8586871B2 · Bernstein et al. · 2013 [cited by applicant]
US 8969154B2 · Sandhu · 2015 [cited by applicant]
US 9520206B2 · Ji et al. · 2016 [cited by applicant]
US 9536953B2 · Elian et al. · 2017 [cited by applicant]
US 9953957B2 · Gao et al. · 2018 [cited by applicant]
US 10217726B1 · Nakano · 2019 [cited by applicant]
US 10319696B1 · Nakano · 2019 [cited by applicant]
US 20060081989A1 · Uang et al. · 2006 [cited by applicant]
US 20060234056A1 · Huang et al. · 2006 [cited by applicant]
US 20060243958A1 · Suh et al. · 2006 [cited by applicant]
US 20070003472A1 · Tolt · 2007 [cited by applicant]
US 20070205792A1 · Mouli et al. · 2007 [cited by applicant]
US 20080087646A1 · Liu et al. · 2008 [cited by applicant]
US 20090266590A1 · Aoi · 2009 [cited by applicant]
US 20100051331A1 · Tsai et al. · 2010 [cited by applicant]
US 20110266694A1 · Sandhu et al. · 2011 [cited by applicant]
US 20120080661A1 · Saito et al. · 2012 [cited by applicant]
US 20120236502A1 · Yamaguchi et al. · 2012 [cited by applicant]
US 20150362266A1 · Liu et al. · 2015 [cited by applicant]
US 20160276281A1 · Sato · 2016 [cited by applicant]
US 20180297849A1 · Liu et al. · 2018 [cited by applicant]
US 20190051592A1 · Kim et al. · 2019 [cited by applicant]
US 20190067253A1 · Nakano · 2019 [cited by applicant]
US 20190172724A1 · Nakano · 2019 [cited by applicant]
US 20190206766A1 · Chandolu · 2019 [cited by examiner]
US 20190378781A1 · Hedrick et al. · 2019 [cited by applicant]
US 20200006290A1 · Chang et al. · 2020 [cited by applicant]
US 20200075524A1 · Seo · 2020 [cited by examiner]
US 20200075532A1 · Hotta et al. · 2020 [cited by applicant]
US 20200098621A1 · Bharath et al. · 2020 [cited by applicant]
CN 1304281A · 2001 [cited by applicant]
CN 1846983A · 2006 [cited by applicant]
CN 101054467A · 2007 [cited by applicant]
CN 102197476A · 2011 [cited by applicant]
CN 102980917A · 2013 [cited by applicant]
CN 103050170A · 2013 [cited by applicant]
CN 104143545A · 2014 [cited by applicant]
CN 108538792A · 2018 [cited by applicant]
JP 07320543A · 1995 [cited by applicant]
JP 2007073388A · 2007 [cited by applicant]
Chinese First Office Action for Chinese Application No. 201911391579.8, dated Feb. 18, 2023, 10 pages with translation. [cited by applicant]
Kim et al., A Role for Graphene in Silicon-Based Semiconductor Devices, Nature, vol. 479, (Nov. 17, 2011), pp. 338-344. [cited by applicant]
Liu et al., Anisotropic Conductive Films Based on Highly Aligned Polyimide Fibers Containing Hybrid Materials of Graphene Nanoribbons and Carbon Nanotubes, Nanoscale, vol. 7, No. 3, (Jan. 21, 2015), pp. 1037-1046 (abstr… [cited by applicant]
Song et al., Highly Anisotropic Thermal Conductivity of Layer-by-Layer Assembled Nanofibrillated Cellulose/Graphene Nanosheets Hybrid Films for Thermal Management, ACS Appl. Mater. Interfaces, vol. 9, No. 3 (Jan. 3, 201… [cited by applicant]
Chinese Second Office Action for Chinese Application No. 201911391579.8, dated Sep. 8, 2023, 2 pages with translation. [cited by applicant]
Lizhen et al., “Production and Application of Carbon Nanotubes”, Science and Technology Review, Jun. 20, 2001, 8 pages, with English Translation. [cited by applicant]
Yurong Liu, “Synthesis and Application of Mesoporous Carbon Materials”, Published on Jun. 2012, 9 pages, with English Translation. [cited by applicant]
Zheng-Quan et al., “Study on Carbon Nanotube Tips for Scanning Tunneling Microscope”, Journal of Chinese Electron Microscopy Society, vol. 20, Oct. 5, 2001, 12 pages, with English Translation. [cited by applicant]