Semiconductor wafer with devices having different top layer thicknesses
A circuit includes a base silicon layer, a base oxide layer, a first top silicon layer, a second top silicon layer, a first semiconductor device, and a second semiconductor device. The base oxide layer is formed over the base silicon layer. The first top silicon layer is formed over a first region of the base oxide layer and has a first thickness. The second top silicon layer is formed over a second region of the base oxide layer and has a second thickness less than the first thickness. The first semiconductor device is formed over the first top silicon layer and the second semiconductor device is formed over the second top silicon layer. The ability to fabricate a top silicon layers with differing thicknesses can provide a single substrate having devices with different characteristics, such as having both fully depleted and partially depleted devices on a single substrate.
1. A circuit comprising:
a base silicon layer;
a base oxide layer formed over the base silicon layer;
a first top silicon layer formed over a first region of the base oxide layer, the first top silicon layer having a first thickness;
a second top silicon layer formed over a second region of the base oxide layer, the second top silicon layer having a second thickness that is less than the first thickness;
a first semiconductor device formed over the first top silicon layer;
a second semiconductor device formed over the second top silicon layer;
a first added oxide formed on the base oxide layer, the first top silicon layer contacting a top surface of the first added oxide and a bottom surface of the first semiconductor device; and
a second added oxide formed on the base oxide layer, the second top silicon layer contacting a top surface of the second added oxide and a bottom surface of the second semiconductor device;
wherein a third thickness of the first added oxide is less than a fourth thickness of the second added oxide.
2. The device of claim 1 , wherein:
the first semiconductor device comprises a partially depleted device and the first thickness is between 500 and 3000 angstroms.
3. The device of claim 1 , wherein:
the second semiconductor device comprises a fully depleted device and the second thickness is between 50 and 500 angstroms.
4. The device of claim 1 , wherein the base oxide layer comprises a buried oxide layer formed of silicon dioxide.
5. The device of claim 1 , further comprising an isolation structure formed between the first semiconductor device and the second semiconductor device, wherein a height of the isolation structure is greater than the first thickness or the second thickness.
6. The device of claim 1 , wherein the isolation structure is formed of at least one of silicon oxide or silicon nitride.
7. The device of claim 1 , wherein the first semiconductor device and the second semiconductor device each include a gate over an active layer.
8. The device of claim 7 , wherein the first semiconductor device and the second semiconductor device each include source and drain regions contacting respective of the active layers.
9. A circuit comprising:
a base silicon layer;
a base oxide layer formed over the base silicon layer;
a first top silicon layer formed over a first region of the base oxide layer, the first top silicon layer having a first thickness;
a second top silicon layer formed over a second region of the base oxide layer, the second top silicon layer having a second thickness that is less than the first thickness;
a first semiconductor device formed over the first top silicon layer;
a second semiconductor device formed over the second top silicon layer, wherein:
the first semiconductor device comprises a partially depleted device and the first thickness is between 500 and 3000 angstroms, and the second semiconductor device comprises a fully depleted device and the second thickness is between 50 and 500 angstroms;
a first added oxide formed on the base oxide layer, the first top silicon layer contacting a top surface of the first added oxide and a bottom surface of the first semiconductor device; and
a second added oxide formed on the base oxide layer, the second top silicon layer contacting a top surface of the second added oxide and a bottom surface of the second semiconductor device;
wherein a height of a bottom surface of the first added oxide is a same as a height of a bottom surface of the second added oxide.
10. The device of claim 9 , wherein the base oxide layer comprises a buried oxide layer formed of silicon dioxide.
11. The device of claim 9 , further comprising an isolation structure formed between the first semiconductor device and the second semiconductor device, wherein a height of the isolation structure is greater than the first thickness or the second thickness.
12. The device of claim 9 , wherein the isolation structure is formed of at least one of silicon oxide or silicon nitride.
13. The device of claim 9 , wherein the first semiconductor device and the second semiconductor device each include a gate over an active layer.
14. The device of claim 13 , wherein the first semiconductor device and the second semiconductor device each include source and drain regions contacting their respective associated active layers.
15. A circuit comprising:
a base silicon layer;
a base oxide layer formed over the base silicon layer;
a first top silicon layer formed over a first region of the base oxide layer, the first top silicon layer having a first thickness;
a second top silicon layer formed over a second region of the base oxide layer, the second top silicon layer having a second thickness that is less than the first thickness;
a third top silicon layer formed over a third region of the base oxide layer, the third top silicon layer having a fifth thickness that is less than the second thickness;
a first semiconductor device formed over the first top silicon layer;
a second semiconductor device formed over the second top silicon layer; and
a third semiconductor device formed over the third top silicon layer;
a first added oxide formed on the base oxide layer, the first top silicon layer contacting a top surface of the first added oxide and a bottom surface of the first semiconductor device; and
a second added oxide formed on the base oxide layer, the second top silicon layer contacting a top surface of the second added oxide and a bottom surface of the second semiconductor device;
wherein a third thickness of the first added oxide is less than a fourth thickness of the second added oxide.
16. The device of claim 15 , wherein:
the first semiconductor device comprises a partially depleted device and the first thickness is between 500 and 3000 angstroms.
17. The device of claim 15 , wherein:
the second semiconductor device comprises a fully depleted device and the second thickness is between 50 and 500 angstroms.
18. The device of claim 15 , wherein the base oxide layer comprises a buried oxide layer formed of silicon dioxide.
19. The device of claim 15 , further comprising an isolation structure formed between the first semiconductor device and the second semiconductor device, wherein a height of the isolation structure is greater than the first thickness or the second thickness.
20. The device of claim 15 , wherein the isolation structure is formed of at least one of silicon oxide or silicon nitride.