Photodiodes
The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and methods of manufacture. The structure includes: a top terminal; an intrinsic material in contact with the top terminal; and a bottom terminal in contact with the intrinsic material, the bottom terminal including a P semiconductor material and a fully depleted N semiconductor material.
1. A structure comprising:
a top terminal comprising P+ semiconductor material;
an intrinsic material touching the top terminal;
a bottom terminal in contact with the intrinsic material, the bottom terminal comprising a P semiconductor material and a fully depleted N semiconductor material; and
an isolation structure above the bottom terminal and an underlying semiconductor substrate, the isolation structure touching the intrinsic material.
2. The structure of claim 1 , wherein the P semiconductor material has a higher dopant concentration than the fully depleted N semiconductor material.
3. The structure of claim 2 , wherein the P semiconductor material and the fully depleted N semiconductor material each comprise Si material.
4. The structure of claim 2 , wherein the P semiconductor material comprises boron doped Si material and the fully depleted N semiconductor material comprises phosphorus doped Si material.
5. The structure of claim 4 , wherein the intrinsic material comprises Ge material.
6. The structure of claim 1 , further comprising a gate structure pinned to the fully depleted N semiconductor material.
7. The structure of claim 6 , wherein the gate structure comprises a source region and a drain region, the drain region being pinned to the fully depleted N semiconductor material.
8. The structure of claim 6 , wherein the bottom terminal is within a substrate material shared with the gate structure and the intrinsic material is within a trench in the substrate material.
9. The structure of claim 6 , wherein the bottom terminal is within a substrate material shared with the gate structure and the intrinsic material is above the substrate material.
10. A structure comprising:
a top terminal comprising P+ semiconductor material;
an intrinsic material touching the top terminal;
a bottom terminal in contact with the intrinsic material, the bottom terminal comprising a P semiconductor material and a fully depleted N semiconductor material;
a shallow trench isolation structure separating the intrinsic material from a drain region of the gate structure; and
a gate structure pinned to the fully depleted N semiconductor material,
wherein the bottom terminal is within a substrate material shared with the gate structure and the intrinsic material is within a trench in the substrate material.
11. The structure of claim 10 , wherein the shallow trench isolation structure is raised above the substrate and the top terminal is above the shallow trench isolation structure.
12. A structure comprising:
a pinned photodiode comprising a fully depleted semiconductor region, and an intrinsic region between an upper p-doped region and a lower n-doped region;
a transistor pinned to the pinned photodiode; and
an isolation structure touching the intrinsic semiconductor material and the lower n-doped region, both above the fully depleted semiconductor region, and separating a drain region of the transistor that is over the lower n-doped region from the intrinsic semiconductor material.
13. The structure of claim 12 , wherein the fully depleted semiconductor region comprises an N semiconductor material between a P semiconductor material and the intrinsic semiconductor region.
14. The structure of claim 13 , wherein the P semiconductor material comprises a higher dopant concentration than the N semiconductor material.
15. The structure of claim 14 , wherein the N semiconductor material and the P semiconductor material are in a substrate material, and the intrinsic semiconductor region is within a trench of the substrate material.
16. The structure of claim 14 , wherein the N semiconductor material and the P semiconductor material are in a substrate material, and the intrinsic region is above the substrate material.
17. A method comprising:
forming a top terminal comprising P+ semiconductor material;
forming an intrinsic material touching the top terminal;
forming a bottom terminal in contact the intrinsic material, the bottom terminal comprising a P semiconductor material and a fully depleted N semiconductor material; and
forming an isolation structure above the bottom terminal and an underlying semiconductor substrate, the isolation structure touching the intrinsic material.
18. A structure comprising:
a top terminal comprising P+ semiconductor material;
an intrinsic material touching the top terminal;
a bottom terminal in contact with the intrinsic material, the bottom terminal comprising a P semiconductor material and a fully depleted N semiconductor material; and
an isolation structure above the bottom terminal, and adjacent to and touching the intrinsic material above and to a side of the bottom terminal, and wherein the bottom terminal touches the intrinsic material.