Structure and methods of forming the structure
View Patent ↗Capacitors, apparatus including a capacitor, and methods for forming a capacitor are provided. One such capacitor may include a first conductor a second conductor above the first conductor, and a dielectric between the first conductor and the second conductor. The dielectric does not cover a portion of the first conductor; and the second conductor does not cover the portion of the first conductor not covered by the dielectric.
1. A device, comprising:
a region comprising memory; and
a peripheral region disposed adjacent to the region configured to supply at least one voltage to the memory, wherein the peripheral region comprises a capacitor, wherein the capacitor comprises a stacked body characterized with a first stair step feature formed from a plurality of conductive levels and a plurality of dielectric levels.
2. The device of claim 1 , wherein the capacitor forms part of a charge pump configured to couple to the memory.
3. The device of claim 1 , wherein the region comprises a plurality of word lines, wherein one or more word lines of the plurality of word lines are separated from at least one adjacent word line of the plurality of word lines by a dielectric level.
4. The device of claim 3 , wherein the plurality of word lines and the plurality of conductive levels comprise a same material.
5. The device of claim 1 , wherein the memory comprises three-dimensional (3D) memory.
6. The device of claim 1 , wherein the region comprises an additional stacked body characterized with a second stair step feature formed from the plurality of conductive levels and the plurality of dielectric levels.
7. The device of claim 6 , wherein the stacked body is able to couple to the additional stacked body via one or more contacts and one or more contact electrodes.
8. The device of claim 6 , wherein the additional stacked body comprises one or more pillar-shaped semiconductor structures forming the memory.
9. The device of claim 6 , wherein the first stair step feature and the second stair step feature are formed at a same time via deposition of the plurality of conductive levels and the plurality of dielectric levels.
10. A method of forming a device, comprising:
forming a region comprising memory; and
forming a peripheral region adjacent to the region including forming at least one capacitor from a plurality of conductive levels and a plurality of dielectric levels that form one or more stair step features of a stacked body.
11. The method of claim 10 , wherein forming the region comprises:
forming the plurality of conductive levels as respective word line levels; and
forming the plurality of dielectric levels, wherein a respective dielectric level of the plurality of dielectric levels are formed between two respective vertically adjacent word line levels.
12. The method of claim 11 , wherein forming the plurality of conductive levels as the respective word line levels comprises depositing material of the plurality of conductive levels in the peripheral region while depositing the material of the plurality of conductive levels in the region.
13. The method of claim 11 , wherein forming the peripheral region comprises:
forming the at least one capacitor at least in part by:
forming a first dielectric level of the plurality of dielectric levels;
forming a first conductive level of the plurality of conductive levels on the first dielectric level; and
removing a portion of the first dielectric level and the first conductive level based on a mask; and
forming a charge pump incorporating the at least one capacitor.
14. The method of claim 13 , wherein the mask is characterized by a width set based on mask slimming.
15. A device, comprising:
a first region comprising memory; and
a second region disposed adjacent to the first region configured to supply at least one voltage to the memory, wherein the second region comprises a first stacked body formation characterized with a first stair step feature formed from a plurality of conductive levels and a plurality of dielectric levels, and wherein the first stacked body formation forms part of a charge pump configured to couple to the memory.
16. The device of claim 15 , wherein an electrical signal delivered to the memory based on the charge pump is generated based on a capacitance of the first stacked body formation.
17. The device of claim 15 , wherein the first region comprises a second stacked body formation characterized with a second stair step feature formed from the plurality of conductive levels and the plurality of dielectric levels.
18. The device of claim 17 , wherein the first stacked body formation is able to couple to the second stacked body formation via one or more contacts and one or more contact electrodes.
19. The device of claim 17 , wherein the second stacked body formation comprises one or more pillar-shaped semiconductor structures configured to store data of the memory.
20. The device of claim 17 , wherein the first stair step feature and the second stair step feature are formed at a same time via deposition of the plurality of conductive levels and the plurality of dielectric levels.