IP Library Granted Patent US 12,321,467
Granted Patent B2
US 12,321,467 · App. 17/854,814 · Granted Jun 3, 2025

Cryptographic computing isolation for multi-tenancy and secure software components

Inventors: Salmin Sultana (Hillsboro, OR); David M. Durham (Beaverton, OR); Michael LeMay (Hillsboro, OR); Karanvir S. Grewal (Hillsboro, OR); Sergej Deutsch (Hillsboro, OR)
Assignee: Intel Corporation
G06F21/602G06F9/30043G06F9/30101G06F21/31G06F21/335G06F21/805
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Quick Facts
Patent No.
US 12,321,467
App. No.
17/854,814
Filed
Jun 30, 2022
Granted
Jun 3, 2025
Kind
B2
Art Unit
2457
USPC
726/26
Abstract

Techniques for cryptographic computing isolation are described. A processor includes circuitry to be coupled to memory configured to store one or more instructions. The circuitry is to execute the one or more instructions to instantiate a first process based on an application. To instantiate the first process is to include creating a context table to be used by the first process, identifying a software component to be invoked during the first process, encrypting the software component using a first cryptographic key, and creating a first entry in the context table. The first entry is to include first context information identifying the encrypted software component and second context information representing the first cryptographic key. In more specific embodiments, third context information representing a first load address of the encrypted software component is stored in the first entry of the context table.

Claims (84)

1. A processor comprising:

circuitry to be coupled to memory configured to store one or more instructions, the circuitry to:

execute the one or more instructions to instantiate a first process based on a request to launch an application associated with two or more software components to be invoked during the first process, wherein to instantiate the first process is to:

create a context table to be used by the first process;

encrypt a first software component of the two or more software components using a first cryptographic key;

encrypt a second software component of the two or more software components using a second cryptographic key, wherein the encrypted second software component includes an encrypted main program of the application;

store, in a first entry in the context table, first context information identifying the encrypted first software component and second context information representing the first cryptographic key; and

store, in a second entry in the context table, fourth context information identifying the encrypted second software component of the application and fifth context information representing the second cryptographic key, wherein subsequent to instantiating the first process, the circuitry is further to:

fetch an encrypted first code block of the encrypted main program from the memory;

decrypt the encrypted first code block of the encrypted main program to generate an unencrypted first instruction; and

execute the unencrypted first instruction to transition from executing the encrypted main program to executing the encrypted first software component.

2. The processor of claim 1 , wherein to instantiate the first process is further to:

store, in the first entry of the context table, third context information representing a first load address of the encrypted first software component.

3. The processor of claim 1 , wherein to instantiate the first process is further to:

create the first entry in the context table in response to determining that the encrypted first software component is shareable with other applications running on the processor.

4. The processor of claim 1 , wherein the second context information is to include either the first cryptographic key or a key handle that references the first cryptographic key.

5. The processor of claim 1 , wherein to instantiate the first process is further to:

populate a first register with a base address of the context table.

6. The processor of claim 1 , wherein to instantiate the first process is further to:

populate a second register with the second cryptographic key; and

populate a third register with a third load address of the encrypted main program.

7. The processor of claim 6 , wherein the encrypted first code block of the encrypted main program is to be decrypted based at least in part on the second cryptographic key in the second register.

8. The processor of claim 6 , wherein the circuitry is further to execute a trusted loader to:

prior to executing the encrypted first software component, encode a return address to an encrypted second instruction in the encrypted main program, wherein the return address is to be encoded with the fourth context information identifying the encrypted main program and a domain switch value to trigger updates to the second register and the third register based on the return address being used to return execution to the encrypted main program.

9. The processor of claim 6 , wherein the circuitry is further to execute a trusted loader to:

prior to executing the encrypted first software component,

update the second register with the first cryptographic key based on the second context information in the first entry of the context table; and

update the third register with a first load address of the encrypted first software component based on third context information in the first entry in the context table.

10. The processor of claim 9 , wherein the circuitry is further to:

subsequent to updating the second register and the third register, fetch an encrypted second code block of the encrypted first software component; and

decrypt the encrypted second code block based at least in part on the first cryptographic key in the second register to generate an unencrypted third instruction of the first software component.

11. The processor of claim 10 , wherein the encrypted second code block of the encrypted first software component is to be decrypted based in part on a second tweak including location information indicating a position of the encrypted second code block relative to the first load address of the encrypted first software component.

12. The processor of claim 1 , wherein the circuitry is further to, during execution of the encrypted first software component in the first process:

initiate a process context switch to pause the first process and activate a second process, wherein the process context switch is to include:

storing a first load address of the encrypted first software component in a first variable of a process control block of the first process;

storing a base address of the context table in a second variable of the process control block of the first process; and

storing the first cryptographic key in a third variable of the process control block of the first process.

13. The processor of claim 1 , wherein the encrypted first software component is position independent code (PIC).

14. The processor of claim 1 , wherein the first software component includes a shared library, a microservice, a function as a service, or a browser component of a browser.

15. The processor of claim 1 , wherein the second first software component includes a shared library, a microservice, a function as a service, or a browser component of a browser.

16. A non-transitory machine readable medium comprising instructions that when executed by a processor, cause the processor to perform operations comprising:

receiving a request to instantiate a first process based on a request to launch an application;

creating a context table for the first process;

loading an encrypted shared library into memory for the first process, wherein the encrypted shared library is encrypted based at least in part on a first cryptographic key;

creating a first entry in the context table;

storing, in the first entry, first context information identifying the encrypted shared library and second context information representing the first cryptographic key;

creating a second entry in the context table, the second entry to include fourth context information identifying an encrypted main program of the application and fifth context information representing a second cryptographic key, wherein the encrypted main program is encrypted based, at least in part, on the second cryptographic key;

populating a first register with a base address of the context table;

populating a second register with the second cryptographic key; and

populating a third register with a load address of the encrypted main program.

17. The non-transitory machine readable medium of claim 16 , wherein the instructions, when executed by the processor, cause the processor to perform further operations comprising:

storing, in the first entry of the context table, third context information representing a first load address of the encrypted shared library.

18. The non-transitory machine readable medium of claim 16 , wherein the instructions, when executed by the processor, cause the processor to perform further operations comprising:

in response to execution of an instruction in the encrypted main program to call the encrypted shared library:

update the second register with the first cryptographic key based on the second context information in the first entry of the context table; and

update the third register with a first load address of the encrypted shared library based on third context information in the first entry of the context table.

19. A system, comprising:

memory for storing a plurality of software components and a main program of a user application; and

a processor coupled to the memory, the processor comprising circuitry to:

instantiate a process based on a request to launch the user application associated with a software component to be invoked during the process, wherein to instantiate the process is to include:

encrypting the main program of the user application based at least in part on a first cryptographic key;

encrypting the software component based at least in part on a second cryptographic key;

storing, in a first entry in a context table of the process, first context information identifying the encrypted main program and second context information representing the first cryptographic key;

storing, in a second entry in the context table of the process, third context information identifying the encrypted software component and fourth context information representing the second cryptographic key,

subsequent to instantiating the process, fetch an encrypted first code block of the encrypted main program from the memory;

decrypt the encrypted first code block of the encrypted main program to generate an unencrypted first instruction; and

execute the unencrypted first instruction to transition from executing the encrypted main program to executing the encrypted first software component.

20. The system of claim 19 , wherein to encrypt the software component is to include:

encrypting an unencrypted second code block of the software component based on the second cryptographic key and a code tweak, wherein the code tweak is to include an offset of the code block relative to a start of the software component.

21. The system of claim 19 , wherein the encrypted software component is position independent code (PIC).

22. A method comprising:

instantiating a first process based on a request to launch an application, wherein the application is associated with a software component to be invoked during the first process, wherein instantiating the first process includes:

encrypting a main program of the application based at least in part on a first cryptographic key;

using at least a second cryptographic key for encrypting the software component to be invoked during the first process;

creating a first entry in a context table of the first process, the first entry to include first context information identifying the main program and second context information representing the first cryptographic key;

creating a second entry in the context table, the second entry to include third context information identifying the software component and fourth context information representing the second cryptographic key;

subsequent to instantiating the first process, fetching an encrypted first code block of the encrypted main program from a memory;

decrypting the encrypted first code block of the encrypted main program to generate an unencrypted first instruction; and

executing the unencrypted first instruction to transition from executing the encrypted main program to executing the encrypted software component.

23. The method of claim 22 , further comprising:

during execution of the encrypted software component in the first process initiate a process context switch to pause the first process and activate a second process, wherein the process context switch includes:

storing a first load address of the encrypted software component in a first variable of a process control block of the first process;

storing a base address of the context table in a second variable of the process control block of the first process; and

storing the second cryptographic key in a third variable of the process control block of the first process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2022
From: SULTANA, SALMIN; DURHAM, DAVID M.; LEMAY, MICHAEL; GREWAL, KARANVIR S.; DEUTSCH, SERGEJ
To: INTEL CORPORATION
Reel/Frame 060373/0047 →
Continuity (1)
Related Publication 20220335140A1 · Oct 20, 2022
References Cited (365)
US 6570989B1 · Ohmori et al. · 2003 [cited by applicant]
US 6961852B2 · Craft · 2005 [cited by applicant]
US 7043016B2 · Roelse · 2006 [cited by applicant]
US 7254718B2 · Kaminaga et al. · 2007 [cited by applicant]
US 7907723B2 · Rubin · 2011 [cited by applicant]
US 8085934B1 · Bhooma · 2011 [cited by applicant]
US 8675868B1 · Yearsley et al. · 2014 [cited by applicant]
US 8798263B2 · Pasini et al. · 2014 [cited by applicant]
US 9015824B1 · Drewry et al. · 2015 [cited by applicant]
US 9135450B2 · Grobman et al. · 2015 [cited by applicant]
US 9213653B2 · Durham et al. · 2015 [cited by applicant]
US 9350534B1 · Poo et al. · 2016 [cited by applicant]
US 9390268B1 · Martini et al. · 2016 [cited by applicant]
US 9436847B2 · Durham et al. · 2016 [cited by applicant]
US 9514285B2 · Durham et al. · 2016 [cited by applicant]
US 9753754B2 · Howell et al. · 2017 [cited by applicant]
US 9811661B1 · Golovkin et al. · 2017 [cited by applicant]
US 9830162B2 · LeMay · 2017 [cited by applicant]
US 9954950B2 · LeMay et al. · 2018 [cited by applicant]
US 9990249B2 · Durham et al. · 2018 [cited by applicant]
US 10084603B2 · Rogers · 2018 [cited by examiner]
US 10216522B2 · LeMay · 2019 [cited by applicant]
US 10326744B1 · Nossik et al. · 2019 [cited by applicant]
US 10387305B2 · Durham et al. · 2019 [cited by applicant]
US 10536266B2 · Courtney · 2020 [cited by applicant]
US 10585809B2 · Durham et al. · 2020 [cited by applicant]
US 10706164B2 · LeMay et al. · 2020 [cited by applicant]
US 10769272B2 · Durham et al. · 2020 [cited by applicant]
US 10785028B2 · Girkar et al. · 2020 [cited by applicant]
US 10860709B2 · LeMay et al. · 2020 [cited by applicant]
US 11216366B2 · Durham et al. · 2022 [cited by applicant]
US 11250165B2 · LeMay et al. · 2022 [cited by applicant]
US 11288188B1 · Tummala et al. · 2022 [cited by applicant]
US 11308225B2 · Kounavis et al. · 2022 [cited by applicant]
US 11321469B2 · Kounavis et al. · 2022 [cited by applicant]
US 11354423B2 · Kounavis et al. · 2022 [cited by applicant]
US 11403234B2 · Durham et al. · 2022 [cited by applicant]
US 11416624B2 · Durham et al. · 2022 [cited by applicant]
US 11575504B2 · Durham et al. · 2023 [cited by applicant]
US 11580035B2 · Durham et al. · 2023 [cited by applicant]
US 11580234B2 · Kounavis et al. · 2023 [cited by applicant]
US 11620391B2 · LeMay et al. · 2023 [cited by applicant]
US 11662928B1 · Kumar · 2023 [cited by examiner]
US 11669625B2 · Durham et al. · 2023 [cited by applicant]
US 11809735B1 · Kumar · 2023 [cited by examiner]
US 11838418B2 · Girkar et al. · 2023 [cited by applicant]
US 12050701B2 · Kounavis et al. · 2024 [cited by applicant]
US 20020065993A1 · Chauvel · 2002 [cited by applicant]
US 20020094081A1 · Medvinsky · 2002 [cited by applicant]
US 20030091185A1 · Swindlehurst et al. · 2003 [cited by applicant]
US 20030101362A1 · Dia · 2003 [cited by applicant]
US 20030126349A1 · Nalawadi et al. · 2003 [cited by applicant]
US 20030149869A1 · Gleichauf · 2003 [cited by applicant]
US 20040034769A1 · Bacha · 2004 [cited by examiner]
US 20040123288A1 · Bennett et al. · 2004 [cited by applicant]
US 20040215895A1 · Cypher · 2004 [cited by applicant]
US 20040268057A1 · Landin et al. · 2004 [cited by applicant]
US 20050010804A1 · Bruening et al. · 2005 [cited by applicant]
US 20050100163A1 · Buer · 2005 [cited by applicant]
US 20060080553A1 · Hall · 2006 [cited by applicant]
US 20070152854A1 · Copley · 2007 [cited by applicant]
US 20070192592A1 · Goettfert et al. · 2007 [cited by applicant]
US 20070201691A1 · Kumagaya · 2007 [cited by applicant]
US 20070220500A1 · Saunier · 2007 [cited by applicant]
US 20080080708A1 · McAlister et al. · 2008 [cited by applicant]
US 20080130895A1 · Jueneman et al. · 2008 [cited by applicant]
US 20080140968A1 · Doshi et al. · 2008 [cited by applicant]
US 20080205651A1 · Goto et al. · 2008 [cited by applicant]
US 20080229425A1 · Perrin et al. · 2008 [cited by applicant]
US 20080263117A1 · Rose et al. · 2008 [cited by applicant]
US 20080288785A1 · Rao et al. · 2008 [cited by applicant]
US 20080320601A1 · Linsley · 2008 [cited by applicant]
US 20090172393A1 · Tanik et al. · 2009 [cited by applicant]
US 20090220071A1 · Gueron et al. · 2009 [cited by applicant]
US 20090249064A1 · Atley et al. · 2009 [cited by applicant]
US 20090254774A1 · Chamdani et al. · 2009 [cited by applicant]
US 20090282393A1 · Costa et al. · 2009 [cited by applicant]
US 20090285390A1 · Scherer et al. · 2009 [cited by applicant]
US 20100023707A1 · Hohmuth et al. · 2010 [cited by applicant]
US 20100122088A1 · Oxford · 2010 [cited by applicant]
US 20100281273A1 · Lee et al. · 2010 [cited by applicant]
US 20110099429A1 · Varma et al. · 2011 [cited by applicant]
US 20110161680A1 · Grube et al. · 2011 [cited by applicant]
US 20110296202A1 · Henry et al. · 2011 [cited by applicant]
US 20120163453A1 · Horowitz · 2012 [cited by applicant]
US 20120284461A1 · Larin et al. · 2012 [cited by applicant]
US 20130191649A1 · Muff et al. · 2013 [cited by applicant]
US 20130232507A1 · Farrugia et al. · 2013 [cited by applicant]
US 20130275766A1 · Plainecassagne et al. · 2013 [cited by applicant]
US 20130283396A1 · Langer et al. · 2013 [cited by applicant]
US 20140020092A1 · Davidov · 2014 [cited by applicant]
US 20140025944A1 · Maletsky et al. · 2014 [cited by applicant]
US 20140149730A1 · Joshi et al. · 2014 [cited by applicant]
US 20140173293A1 · Kaplan · 2014 [cited by applicant]
US 20140270159A1 · Youn et al. · 2014 [cited by applicant]
US 20150032996A1 · Koeberl et al. · 2015 [cited by applicant]
US 20150234728A1 · Coleman et al. · 2015 [cited by applicant]
US 20150244518A1 · Koo et al. · 2015 [cited by applicant]
US 20150371063A1 · Van Antwerpen et al. · 2015 [cited by applicant]
US 20150378941A1 · Rozas et al. · 2015 [cited by applicant]
US 20150381358A1 · Grobman et al. · 2015 [cited by applicant]
US 20160056954A1 · Lee et al. · 2016 [cited by applicant]
US 20160092702A1 · Durham et al. · 2016 [cited by applicant]
US 20160094552A1 · Durham et al. · 2016 [cited by applicant]
US 20160104009A1 · Henry et al. · 2016 [cited by applicant]
US 20160154963A1 · Kumar et al. · 2016 [cited by applicant]
US 20160188889A1 · Trivedi et al. · 2016 [cited by applicant]
US 20160192194A1 · Yang · 2016 [cited by examiner]
US 20160285892A1 · Kishinevsky et al. · 2016 [cited by applicant]
US 20160292422A1 · Hayashi et al. · 2016 [cited by applicant]
US 20160335187A1 · Greenspan et al. · 2016 [cited by applicant]
US 20160364341A1 · Banginwar et al. · 2016 [cited by applicant]
US 20160364707A1 · Varma · 2016 [cited by applicant]
US 20160371496A1 · Sell · 2016 [cited by applicant]
US 20160380772A1 · Gopal et al. · 2016 [cited by applicant]
US 20170026171A1 · Lal et al. · 2017 [cited by applicant]
US 20170063532A1 · Bhattacharyya et al. · 2017 [cited by applicant]
US 20170063547A1 · Brandt et al. · 2017 [cited by applicant]
US 20170093567A1 · Gopal et al. · 2017 [cited by applicant]
US 20170171185A1 · Camenisch · 2017 [cited by examiner]
US 20170177368A1 · DeHon et al. · 2017 [cited by applicant]
US 20170235957A1 · Maletsky · 2017 [cited by applicant]
US 20170237560A1 · Mueller et al. · 2017 [cited by applicant]
US 20170249260A1 · Sahita et al. · 2017 [cited by applicant]
US 20170285976A1 · Durham et al. · 2017 [cited by applicant]
US 20170300425A1 · Meredith et al. · 2017 [cited by applicant]
US 20170308297A1 · Roberts et al. · 2017 [cited by applicant]
US 20170344297A1 · Woolman et al. · 2017 [cited by applicant]
US 20170364704A1 · Wright et al. · 2017 [cited by applicant]
US 20180046576A1 · Lesartre et al. · 2018 [cited by applicant]
US 20180046823A1 · Durham et al. · 2018 [cited by applicant]
US 20180082057A1 · LeMay et al. · 2018 [cited by applicant]
US 20180095812A1 · Deutsch et al. · 2018 [cited by applicant]
US 20180095899A1 · Durham et al. · 2018 [cited by applicant]
US 20180095906A1 · Doshi et al. · 2018 [cited by applicant]
US 20180109508A1 · Wall et al. · 2018 [cited by applicant]
US 20180247082A1 · Durham et al. · 2018 [cited by applicant]
US 20180268170A1 · Li et al. · 2018 [cited by applicant]
US 20180287785A1 · Pfannenschmidt et al. · 2018 [cited by applicant]
US 20180365069A1 · Nemiroff et al. · 2018 [cited by applicant]
US 20190026236A1 · Barnes · 2019 [cited by applicant]
US 20190042369A1 · Deutsch et al. · 2019 [cited by applicant]
US 20190042481A1 · Feghali et al. · 2019 [cited by applicant]
US 20190042734A1 · Kounavis et al. · 2019 [cited by applicant]
US 20190042766A1 · Pappachan et al. · 2019 [cited by applicant]
US 20190042796A1 · Bokern et al. · 2019 [cited by applicant]
US 20190042799A1 · Durham et al. · 2019 [cited by applicant]
US 20190044927A1 · Sood et al. · 2019 [cited by applicant]
US 20190044954A1 · Kounavis et al. · 2019 [cited by applicant]
US 20190045016A1 · Dewan et al. · 2019 [cited by applicant]
US 20190050558A1 · LeMay et al. · 2019 [cited by applicant]
US 20190087354A1 · Chhabra et al. · 2019 [cited by applicant]
US 20190095350A1 · Durham et al. · 2019 [cited by applicant]
US 20190097794A1 · Nix · 2019 [cited by applicant]
US 20190102322A1 · Chhabra et al. · 2019 [cited by applicant]
US 20190102567A1 · LeMay et al. · 2019 [cited by applicant]
US 20190102577A1 · Gueron et al. · 2019 [cited by applicant]
US 20190147192A1 · Khosravi et al. · 2019 [cited by applicant]
US 20190220625A1 · Durham et al. · 2019 [cited by applicant]
US 20190227951A1 · Durham et al. · 2019 [cited by applicant]
US 20190319781A1 · Chhabra et al. · 2019 [cited by applicant]
US 20190339978A1 · Wallach · 2019 [cited by applicant]
US 20190347445A1 · Chen · 2019 [cited by applicant]
US 20190354726A1 · Critelli et al. · 2019 [cited by applicant]
US 20190377574A1 · Weimer · 2019 [cited by applicant]
US 20200004953A1 · LeMay et al. · 2020 [cited by applicant]
US 20200007332A1 · Girkar et al. · 2020 [cited by applicant]
US 20200050553A1 · Hajj et al. · 2020 [cited by applicant]
US 20200076585A1 · Sheppard et al. · 2020 [cited by applicant]
US 20200089430A1 · Kanno · 2020 [cited by applicant]
US 20200117810A1 · Kounavis et al. · 2020 [cited by applicant]
US 20200125501A1 · Durham et al. · 2020 [cited by applicant]
US 20200125502A1 · Durham et al. · 2020 [cited by applicant]
US 20200125742A1 · Kounavis et al. · 2020 [cited by applicant]
US 20200125769A1 · Kounavis et al. · 2020 [cited by applicant]
US 20200125770A1 · LeMay et al. · 2020 [cited by applicant]
US 20200134234A1 · LeMay et al. · 2020 [cited by applicant]
US 20200145187A1 · Kounavis et al. · 2020 [cited by applicant]
US 20200145199A1 · Kounavis et al. · 2020 [cited by applicant]
US 20200159676A1 · Durham et al. · 2020 [cited by applicant]
US 20200169383A1 · Durham et al. · 2020 [cited by applicant]
US 20200201789A1 · Durham et al. · 2020 [cited by applicant]
US 20200241775A1 · Breslow · 2020 [cited by applicant]
US 20200249995A1 · Wong et al. · 2020 [cited by applicant]
US 20200257827A1 · Kounavis et al. · 2020 [cited by applicant]
US 20200379902A1 · Durham et al. · 2020 [cited by applicant]
US 20200380140A1 · Medwed et al. · 2020 [cited by applicant]
US 20200382289A1 · Xue et al. · 2020 [cited by applicant]
US 20200382303A1 · Girkar et al. · 2020 [cited by applicant]
US 20210004470A1 · Babic et al. · 2021 [cited by applicant]
US 20210058379A1 · Bursell et al. · 2021 [cited by applicant]
US 20210117340A1 · Trikalinou et al. · 2021 [cited by applicant]
US 20210117342A1 · Durham · 2021 [cited by applicant]
US 20210149825A1 · Durham et al. · 2021 [cited by applicant]
US 20210150040A1 · Durham et al. · 2021 [cited by applicant]
US 20210200673A1 · Gupta et al. · 2021 [cited by applicant]
US 20210218547A1 · Weiler et al. · 2021 [cited by applicant]
US 20210240638A1 · Deutsch et al. · 2021 [cited by applicant]
US 20210405896A1 · Durham et al. · 2021 [cited by applicant]
US 20220012188A1 · Durham et al. · 2022 [cited by applicant]
US 20220019698A1 · Durham et al. · 2022 [cited by applicant]
US 20220138329A1 · Kounavis et al. · 2022 [cited by applicant]
US 20220156180A1 · Durham et al. · 2022 [cited by applicant]
US 20220197638A1 · LeMay · 2022 [cited by applicant]
US 20220206958A1 · LeMay et al. · 2022 [cited by applicant]
US 20220300626A1 · Kounavis et al. · 2022 [cited by applicant]
US 20220382885A1 · Durham et al. · 2022 [cited by applicant]
US 20230027329A1 · Durham · 2023 [cited by examiner]
US 20240104027A1 · Ghosh et al. · 2024 [cited by applicant]
DE 102018125786A1 · 2019 [cited by applicant]
EP 2073430A1 · 2009 [cited by applicant]
EP 3326102A1 · 2018 [cited by applicant]
EP 3745273A1 · 2020 [cited by applicant]
JP 2009139899A · 2009 [cited by applicant]
JP 2011522469A · 2011 [cited by applicant]
JP 2013541783A · 2013 [cited by applicant]
JP 2019091430A · 2019 [cited by applicant]
KR 101754518B1 · 2017 [cited by applicant]
WO 2013147794A1 · 2013 [cited by applicant]
WO 2014059438A2 · 2014 [cited by applicant]
WO 2017014885A1 · 2017 [cited by applicant]
WO WO2021162792A1 · 2021 [cited by examiner]
WO 2022139850 · 2022 [cited by applicant]
U.S. Appl. No. 17/855,261, filed Jun. 30, 2022. [cited by applicant]
U.S. Appl. No. 17/791,000, filed Jul. 6, 2022. [cited by applicant]
“Armv8.5-A Memory Tagging Extension White Paper”, Oct. 9, 2019, accessed at https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Arm_Memory_Tagging_Extension_Whitepaper.pdf, 9 pages. [cited by applicant]
Ainsworth, Sam et al., “MarkUs: Drop-in use-after-free prevention for low-level languages,” 2020 IEEE Symposium on Security and Privacy, Cambridge, UK (14 pages). [cited by applicant]
Andreatos et al., “A comparison of random number sequences for image encryption”, Mathematical Methods in Science and Engineering, 2014, pp. 146-151 (Year: 2014) (7 pages). [cited by applicant]
Avanzi, Roberto, “The QARMA Block Ciper Family, Almost MDS Matrices Over Rings With Zero Divisors, Nearly Symmetric Even-Mansour Constructions With Non-Involutory Central Rounds, and Search Heuristics for Low-Latency S-… [cited by applicant]
Beaulieu, Ray et al., “Simon and Spec: Block Ciphers for the Internet of Things,” National Security Agency, Jul. 2015 (15 pages). [cited by applicant]
Bernstein, Daniel J., “Gimli,” Sep. 27, 2019, retrieved from https://csrc.nist.gov/CSRC/media/Projects/lightweight-cryptography/documents/round-2/spec-doc-rnd2/gimli-spec-round2.pdf, (48 pages). [cited by applicant]
BiiN, “CPU Architecture Reference Manual”, accessed at http://bitsavers.informatik.uni-stuttgart.de/pdf/biin/BiIN_CPU_Architecture_Reference_Man_Jul88. pdf, Jul. 1988, 401 pages. [cited by applicant]
Boivie, Rick, IBM Research Report, SecureBlue++: CPU Support for Secure Execution, May 23, 2012, available online at https://domino.research.ibm.com/library/cyberdig.nsf/papers/E605BDC5439097F085257A13004D25CA/$File/rc2… [cited by applicant]
Borghoff, Julia et al., “Prince—A Low-Latancy Block Ciper for Pervasive Computing Applications,” Advances in Cryptology—Asiacrypt 2012—18th International Conference on the Theory and Application of Cryptology and Inform… [cited by applicant]
Carlini, Nicholas, et al.; “Control-Flow Bending: On the Effectiveness of Control-Flow Integrity,” Proceedings of the 24th USENIX Security Symposium; Washington, D.C.; Aug. 2015; 16 pages. [cited by applicant]
Carr, Scott A. et al., “DataShield: Configurable Data Confidentiality and Integrity,” Purdue University, Asia CCS, '17, Apr. 2-6, 2017, Abu Dhabi, United Arab Emirates (12 pages). [cited by applicant]
Chen, Tony et al., “Pointer Tagging for Memory Safety.” Microsoft. Retrieved from https://www.microsoft.com/en-us/research/uploads/prod/2019/07/Pointer-Tagging-for-Memory-Safety.pdf, 23 pages. [cited by applicant]
Durham, David M. et al; U.S. Appl. No. 17/539,933, filed Dec. 1, 2021. [cited by applicant]
Dutch Office Action received in Application No. 2029792, dated Mar. 22, 2023, with Statement of Relevance, 15 pages. [cited by applicant]
Dworkin, Morris, “Recommendation for Block Cipher Modes of Operation: The XTS-AES Mode for Confidentiality on Storage Devices,” NIST Special Publication 800-38E, Jan. 2010, available online at https://nvlpubs.nist.gov/n… [cited by applicant]
EPO Communication Pursuant to Article 94(3) EPC in EP Application Serial No. 20181907.5-1218 mailed on Mar. 27, 2023 (6 pages). [cited by applicant]
EPO European Extended Search Report in EP Application Serial No. 20918345.8 mailed on Mar. 14, 2024, 7 pages. [cited by applicant]
EPO; Extended European Search Report issued in EP Patent Application No. 20163534.9, dated Sep. 24, 2020; 8 pages. [cited by applicant]
EPO; Extended European Search Report issued in EP Patent Application No. 20163546.3, dated Sep. 28, 2020; 8 pages. [cited by applicant]
EPO; Extended European Search Report issued in EP Patent Application No. 20163670.1, dated Sep. 29, 2020; 8 pages. [cited by applicant]
EPO; Extended European Search Report issued in EP Patent Application No. 20163907.7, dated Oct. 6, 2020; 9 pages. [cited by applicant]
EPO; Extended European Search Report issued in EP Patent Application No. 20164326.9, dated Oct. 2, 2020; 9 pages. [cited by applicant]
EPO; Extended European Search Report issued in EP Patent Application No. 20164636.1, dated Oct. 6, 2020; 8 pages. [cited by applicant]
EPO; Extended European Search Report issued in EP Patent Application No. 20168972.6, dated Jul. 3, 2020; 9 pages. [cited by applicant]
EPO; Extended European Search Report issued in EP Patent Application No. 20181907.5, dated Nov. 2, 2020; 9 pages. [cited by applicant]
EPO; Extended European Search Report issued in EP Patent Application No. 20193625.9, dated Feb. 22, 2021; 7 pages. [cited by applicant]
EPO; Extended European Search Report issued in EP Patent Application No. 20210029.3, dated May 20, 2021; 8 pages. [cited by applicant]
EPO; Extended European Search Report issued in EP Patent Application No. 21195529.9, dated Mar. 1, 2022; 6 pages. [cited by applicant]
EPO; Extended European Search Report issued in EP Patent Application No. 21196104.0, dated Feb. 15, 2022; 10 pages. [cited by applicant]
EPO; Extended European Search Report issued in EP Patent Application No. 22153425.8, dated Jul. 18, 2022; 8 pages. [cited by applicant]
EPO; Extended European Search Report issued in European Patent Application No. EP 20163095.1, dated Aug. 10, 2020; 9 pages. [cited by applicant]
EPO; Extended European Search Report issued in Patent Application No. EP 20163518.2, dated Aug. 19, 2020; 10 pages. [cited by applicant]
EPO; Extended European Search Report issued in Patent Application No. EP 20163661.0, dated Aug. 17, 2020; 9 pages. [cited by applicant]
EPO; Office Action issued in EP Patent Application No. 20210029.3, dated Mar. 16, 2022; 4 pages. [cited by applicant]
Filardo, Nathaniel Wesley et al., “Cornucopia: Temporal Safety for CHERI Heaps;” Cambridge, UK. (18 pages). [cited by applicant]
France Intellectual Property Office; Office Action issued in FR2114288, dated Nov. 28, 2023; 4 pages with English translation. [cited by applicant]
France Intellectual Property Office; Search Report issued in FR2114288, dated Jan. 12, 2023; 24 pages with English translation. [cited by applicant]
French Office Action received in Application No. 2114288, dated Apr. 3, 2024, with English translation, 6 pages. [cited by applicant]
Gallagher, Mark et al., “Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defenses with Churn,” ASPLOS '19, Apr. 13-17, 2019, pp. 469-484, available online at https://web.eecs.u… [cited by applicant]
Gallagher, Mark, Slide Deck entitled “Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defenses with Churn,” ASPLOS '19, Apr. 13-17, 2019, retrieved from https://twd2.me/wp-cont… [cited by applicant]
GitHub.com; “V8 Garbage Collector,” Oct. 23, 2018 (13 pages). [cited by applicant]
Haraken@, et al.,; “MTECheckedPtr” Last updated Jul. 9, 2020; Accessed Jul. 19, 2022; Retrieved from https://docs.google.com/document/d/1ph7iOorkGqTuETFZp-xvHV4L2rYootuz1ThzAAoGe30/edit#heading=h.b57m9s7iv7yr; 9 pages. [cited by applicant]
Haraken@; “CheckedPtr2 and CheckedPtr3,” retrieved from the Internet at https://docs.google.com/document/d/14TsvTgswPUOQuQol9TmkFQnuSaFD8ZLHRvzapNwl5vs; published Apr. 4, 2020; 8 pages. [cited by applicant]
Hong, H. et al., “Data-Oriented Programming: On the Expressiveness of Non-Control Data Attacks,” IEEE S&P, 18 pages, 2016. [cited by applicant]
Intel 64 and IA-32 Architectures Developer's Manual, vol. 3A: System Programming Guide, Part 1, retrieved from https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-develope… [cited by applicant]
Intel; “Intel 64 and IA-32 Architectures Software Developer's Manual,” vol. 1: Basic Architecture, Chapter 3: Basic Execution Environment; Oct. 2019; 57 pages. [cited by applicant]
Intel; “Intel 64 and IA-32 Architectures Software Developer's Manual,” vol. 1: Basic Architecture, Chapter 6: Procedure Calls, Interrupts, and Exceptions; Oct. 2019; 48 pages. [cited by applicant]
Intel; “Intel 64 and IA-32 Architectures Software Developer's Manual,” vol. 3: System Programming Guide, Chapter 6; Oct. 2019; 110 pages. [cited by applicant]
Intel® 64 and IA-32 Architectures Software Developer's Manual, vol. 2B: Instruction Set Reference, M-U, Sep. 2016, retrieved from https://www.intel.com/content/dam/www/public/US/en/documents/manuals/64-ia-32-architectur… [cited by applicant]
Intel® 64 and IA-32 Architectures Software Developer's Manual, vol. 3D: System Programming Guide, Part 4, Sep. 2016, 224 pages, retrieved from https://www.intel.com/content/dam/www/public/US/en/documents/manuals/64-ia-3… [cited by applicant]
Non-Final Office Action received in U.S. Appl. No. 16/998,913, dated Jan. 25, 2023, 13 pages. [cited by applicant]
Non-Final Office Action received in U.S. Appl. No. 17/472,272, dated Jul. 7, 2023, 11 pages. [cited by applicant]
Notice of Allowance, U.S. Appl. No. 16/024,259, May 20, 2020, 20 pages. [cited by applicant]
Notice of Allowance, U.S. Appl. No. 16/728,928, Feb. 22, 2021, 10 pages. [cited by applicant]
Notice of Allowance, U.S. Appl. No. 17/321,087, Apr. 13, 2022, 13 pages. [cited by applicant]
Notice of Allowance, U.S. Appl. No. 17/321,087, May 4, 2022, 9 pages. [cited by applicant]
U.S. Appl. No. 17/953,186; filed Sep. 26, 2022 . [cited by applicant]
USPTO Final Office Action for U.S. Appl. No. 17/481,405 received on Aug. 30, 2023, entitled, Cryptographic Computing Including Enhanced Cryptographic Addresses (21 pages). [cited by applicant]
USPTO Final Office Action for U.S. Appl. No. 17/485,213 received on Aug. 8, 2023, entitled, Object and Cacheline Granularity Cryptographic Memory Integrity (19 pages). [cited by applicant]
USPTO Final Office Action in U.S. Appl. No. 16/724,059 mailed on Sep. 2, 2022 (34 pages). [cited by applicant]
USPTO Final Office Action in U.S. Appl. No. 17/576,533 mailed on May 30, 2023 (9 pages). [cited by applicant]
USPTO Final Office Action in U.S. Appl. No. 17/833,515 mailed on Sep. 25, 2023 (24 pages). [cited by applicant]
USPTO Non-Final Office Action for U.S. Appl. No. 17/481,405 received on Feb. 16, 2023, entitled, Cryptographic Computing Including Enhanced Cryptographic Addresses (19 pages). [cited by applicant]
USPTO Non-Final Office Action for U.S. Appl. No. 17/485,213 received on Feb. 14, 2023, entitled, Object and Cacheline Granularity Cryptographic Memory Integrity (19 pages). [cited by applicant]
USPTO Non-Final Office Action for U.S. Appl. No. 17/539,933, filed Dec. 1, 2021 entitled, Security Check Systems and Methods for Memory Allocations (5 pages). [cited by applicant]
USPTO Non-Final Office Action in U.S. Appl. No. 16/709,612 mailed on Feb. 17, 2022 (17 pages). [cited by applicant]
USPTO Non-Final Office Action in U.S. Appl. No. 16/720,059 mailed on Jan. 21, 2022 (20 pages). [cited by applicant]
USPTO Non-Final Office Action in U.S. Appl. No. 16/722,342 mailed on Aug. 29, 2022 (14 pages). [cited by applicant]
USPTO Non-Final Office Action in U.S. Appl. No. 16/723,871 mailed on Nov. 10, 2022 (11 pages). [cited by applicant]
USPTO Non-Final Office Action in U.S. Appl. No. 16/723,927 dated Jun. 8, 2021 (32 pages). [cited by applicant]
USPTO Non-Final Office Action in U.S. Appl. No. 16/723,977 mailed on Aug. 3, 2021 (37 pages). [cited by applicant]
USPTO Non-Final Office Action in U.S. Appl. No. 16/724,105 mailed on Jul. 13, 2021 (10 page). [cited by applicant]
USPTO Non-Final Office Action in U.S. Appl. No. 16/740,359 mailed on Sep. 27, 2021 (8 pages). [cited by applicant]
USPTO Non-Final Office Action in U.S. Appl. No. 16/862,022 mailed on Jun. 20, 2023 (12 pages). [cited by applicant]
USPTO Non-Final Office Action in U.S. Appl. No. 17/134,405 mailed on Aug. 1, 2022 (15 pages). [cited by applicant]
USPTO Non-Final Office Action in U.S. Appl. No. 17/134,406 mailed on Jan. 21, 2022 (11 pages). [cited by applicant]
USPTO Non-Final Office Action in U.S. Appl. No. 17/576,533 mailed on Feb. 7, 2023 (8 pages). [cited by applicant]
USPTO Non-Final Office Action in U.S. Appl. No. 17/833,515 mailed on Apr. 14 (23 pages). [cited by applicant]
USPTO Notice of Allowance for U.S. Appl. No. 16/998,913 received Aug. 7, 2023 (13 pages). [cited by applicant]
USPTO Notice of Allowance for U.S. Appl. No. 17/485,213 received Dec. 14, 2023 (6 pages). [cited by applicant]
USPTO Notice of Allowance for U.S. Appl. No. 17/539,933 received Jun. 16, 2023 entitled, Security Check Systems and Methods for Memory Allocations (7 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 16/709,612 mailed on Aug. 23, 2022 (18 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 16/709,612 mailed on Nov. 25, 2022 (14 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 16/722,342 mailed on Apr. 24, 2023 (4 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 16/722,342 mailed on Feb. 23, 2023 (7 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 16/722,342 mailed on Jul. 13, 2023 (7 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 16/722,707 mailed on Mar. 28, 2022 (10 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 16/723,468 mailed on Oct. 18, 2021 (10 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 16/723,871 mailed on May 26, 2023 (7 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 16/723,927 dated Dec. 24, 2021 (13 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 16/723,977 mailed on Feb. 3, 2022 (13 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 16/724,026 mailed on Aug. 10, 2022 (9 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 16/724,026 mailed on Dec. 7, 2022 (14 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 16/724,105 dated Nov. 16, 2021 (9 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 16/724,105 mailed on Mar. 31, 2022 (8 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 16/740,359 mailed on Mar. 22, 2022 (9 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 16/776,467 mailed on Jul. 18, 2022 (10 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 16/776,467 mailed on Nov. 9, 2022 (8 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 17/134,405 mailed on Jan. 31, 2023 (8 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 17/134,406 mailed on Oct. 5, 2022 (10 pages). [cited by applicant]
International Preliminary Report on Patentability for International Patent Application No. PCT/US2020/067076, mailed Jul. 6, 2023; 7 pages. [cited by applicant]
Japanese Office Action received in Application No. 2022-540601, dated Sep. 3, 2024, with English translation, 6 pages. [cited by applicant]
Kim, Yonghae, et al.; “Hardware-based Always-On Heap Memory Safety,” 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO); Athens, Greece; 14 pages. [cited by applicant]
Kroes et al., Fast and Generic Metadata Management with Mid-Fat Pointers, 2017, ACM, 6 pages (Year: 2017). [cited by applicant]
Kwon, Albert et al., “Low-Fat Pointers: Compact Encoding and Efficient Gate-Level Implementation of Fat Pointers for Spatial Safety and Capability-based Security,” CCS' 13: Proceedings of the 2013 ACM SIGSAC Conference … [cited by applicant]
L. Fiorin, G. Palermo, S. Lukovic, V. Catalano and C. Silvano, “Secure Memory Accesses on Networks-on-Chip,” in IEEE Transactions on Computers, vol. 57, No. 9, pp. 1216-1229, Sep. 2008, doi: 10.1109/TC.2008.69; 14 pages. [cited by applicant]
L. Muscariello et al., “Hybrid Information-Centric Networking draft-muscariello-intarea-hicn-00,” Cisco Systems, Inc., Jun. 7, 2018 (21 pages). [cited by applicant]
Lilijestrand, Hans et al. “PACStack: an Authenticated Call Stack,” Sep. 3, 2019, retrieved from https://arxiv.org/pdf/1905.10242.pdf, (20 pages). [cited by applicant]
Liljestrand, Hans, et al., “PAC it up: Towards Pointer Integrity using ARM Pointer Authentication”, accessed at https://arxiv.org/pdf/1811.09189.pdf, last updated May 24, 2019, 21 pages. [cited by applicant]
Mohamed et al., “A scheme for implementing address translation storage buffers,” Proceedings of the 2002 IEEE Canadian Conference on Electrical and Computer Engineering, 2002, pp. 626-632. [cited by applicant]
Myoung Jin Nam, Periklis Akritidis, and David J Greaves. 2019. Framer: a tagged-pointer capability system with memory safety applications. In Proceedings of the 35th Annual Computer Security Applications Conference (ACS… [cited by applicant]
Nasahl, Pascal et al., “CrypTag: Thwarting Physical and Logical Memory Vulnerabilities using Cryptographically Colored Memory”, https://doi .org/10.48550/arXiv.2012.06761, ARXIV ID: 2012.06761, Dec. 12, 2020. (13 pages). [cited by applicant]
Neagu, Madalin, et al.; “Increasing Memory Security Through Data Scrambling and Information Entropy Models,” 2014 IEEE 15th International Symposium on Computational Intelligence and Informatics; Nov. 2014; 5 pages. [cited by applicant]
PCT International Preliminary Report on Patentability issued in PCT/US2020/067072, dated Aug. 25, 2022; 8 pages. [cited by applicant]
PCT International Search Report and Written Opinion issued in PCT/US2020/067072, dated May 26, 2021; 13 pages. [cited by applicant]
PCT International Search Report and Written Opinion issued in PCT/US2020/067076, dated Sep. 9, 2021; 11 pages. [cited by applicant]
Pyo, Changwoo, “Encoding Function Pointers and Memory Arrangement Checking against Buffer Overflow Attack,” In Proceedings of the 4th International Conference on Information and Communications Security (ICICS 2002) (12 … [cited by applicant]
Qualcomm Technologies, Inc., “Pointer Authentication on ARMv8.3, Design and Analysis of the New Software Security Instructions,” Jan. 2017, retrieved from https://www.qualcomm.com/media/documents/files/whitepaper-pointe… [cited by applicant]
Savry, Olivier, et al., “Intrinsec, an Intrinsically Secure Processor”, Risc V Workshop, Dec. 6, 2019, accessed at: http://riscv.org/wp-content/uploads/2019/06/16.15-CEA-RISC-V-Workshop-Zurich.pdf, (15 pages.). [cited by applicant]
Serebryany, Kostya, “ARM Memory Tagging Extension and How it Improves C/C++ Memory Safety,” Summer 2019, (5 pages). [cited by applicant]
The Electronics Resurgence Initiative, “SSITH: TA1 (Hardware) Performers,” Dec. 22, 2018, available online at https://eri-summit.darpa.mil/docs/ERIPoster_Applications_SSITH_DARPA.pdf, (1 page). [cited by applicant]
Tuck, Nathan et al., “Hardware and Binary Modification Support for Code Pointer Protection From Buffer Overflow,” 37th International Symposium on Microarchitecture (MICRO-37'04), 2004, pp. 209-220 (12 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 17/833,515 mailed on Apr. 2, 2024 (9 pages). [cited by applicant]
USPTO Restriction Requirement in U.S. Appl. No. 16/862,022 mailed on Feb. 2, 2023 (6 pages). [cited by applicant]
USPTO Supplemental Notice of Allowance in U.S. Appl. No. 16/722,707 mailed on Apr. 8, 2022 (5 pages). [cited by applicant]
USPTO; Notice of Allowance issued in U.S. Appl. No. 17/472,272, dated Jan. 9, 2024, 9 pages [cited by applicant]
Watson et al., Capability Hardware Enhanced RISC Instructions (CHERI): Notes on the Meltdown and Spectre Attacks, University of Campbridge Computer Laboratory, Feb. 2018, 16 pages. [cited by applicant]
Watson, Robert N.M., et al., “An Introduction to CHERI”, Technical Report UCAM-CL-TR-941, University of Cambridge Computer Labratory, Cambridge, United Kingdom, Sep. 2019, 43 pages. [cited by applicant]
Watson, Robert N.M., et al., “Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 8),” University of Cambridge Computer Laboratory Technical Report No. 951, Cambridge, UK; Oct. 20… [cited by applicant]
Watson, Robert N.M., et al., “Cheri: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization”, 2015 IEEE Symposium on Security and Privacy, May 2015, accessed at https://discovery.ucl.ac.uk/id… [cited by applicant]
Whelihan, David et al., “A Key-Centric Processor Architecture for Secure Computing,” 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2016, pp. 173-178. (6 pages). [cited by applicant]
Xia, Hongyan et al., “CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety, ” MICRO-52, Oct. 2019, Columbus, OH, US (13 pages). [cited by applicant]
Xu, Leslie et al., “White Paper, Securing the Enterprise with Intel AES-NI, Intel Advanced Encryption Standard New Instructions (AES-NI),” Intel Corporation, Version, 2.0, Sep. 2010 (13 pages). [cited by applicant]
Yan, Z., et al., “Hardware translation coherence for virtualized systems,” 2017 3 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA), 2017, pp. 430-443, doi: 10.1145/3079856.3080211. {Year: 201… [cited by applicant]
Yang, Jun et al., “Improving Memory Encryption Performance in Secure Processors,” IEEE Transactions on Computers, vol. 54, No. 5, May 2005 (11 pages). [cited by applicant]
Zhu, Ge et al., “Protection against indirect overflow attacks on pointers,” Second IEEE International Information Assurance Workshop, 2004. Proceedings., 2004, pp. 97-106. (10 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 17/855,261 mailed on Oct. 29, 2024 (10 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 17/878,322 mailed on Dec. 18, 2024 (10 pages). [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 17/855,261, dated Jan. 16, 2025; 9 pages. [cited by applicant]
USPTO Notice of Allowance in U.S. Appl. No. 18/499,133 mailed on Feb. 26, 2025; 7 pages. [cited by applicant]