Metal gates for multi-gate devices and fabrication methods thereof
An n-type field effect transistor includes semiconductor channel members vertically stacked over a substrate, a gate dielectric layer wrapping around each of the semiconductor channel members, and a work function layer disposed over the gate dielectric layer. The work function layer wraps around each of the semiconductor channel members. The n-type field effect transistor also includes a WF isolation layer disposed over the WF layer and a gate metal fill layer disposed over the WF isolation layer. The WF isolation layer fills gaps between adjacent semiconductor channel members.
1. An n-type field effect transistor, comprising:
semiconductor channel members vertically stacked over a substrate;
a gate dielectric layer wrapping around each of the semiconductor channel members;
a first work function (WF) layer disposed over the gate dielectric layer and wrapping around each of the semiconductor channel members;
a first WF isolation layer disposed over the first WF layer and filling gaps between adjacent semiconductor channel members;
a second WF layer disposed over the first WF isolation layer;
a second WF isolation layer disposed over the second WF layer, wherein the second WF isolation layer is a metal alloy nitride layer; and
a gate metal fill layer disposed over the second WF isolation layer.
2. The n-type field effect transistor of claim 1 , wherein the first WF isolation layer includes semiconductive material.
3. The n-type field effect transistor of claim 2 , wherein the semiconductive material is amorphous silicon.
4. The n-type field effect transistor of claim 2 , wherein the semiconductive material is polysilicon.
5. The n-type field effect transistor of claim 1 , wherein the gate metal fill layer is not disposed in the gaps.
6. The n-type field effect transistor of claim 1 , wherein a thickness of the first WF isolation layer disposed over sidewall surfaces of the semiconductor channel members is smaller than a thickness of the first WF isolation layer disposed in the gaps.
7. The n-type field effect transistor of claim 1 , wherein a thickness of the first WF isolation layer disposed over sidewall surfaces of the semiconductor channel members is larger than a thickness of the first WF isolation layer disposed in the gaps.
8. The n-type field effect transistor of claim 1 , wherein the first and second WF layers are of opposite conductive types.
9. A semiconductor device, comprising:
a substrate having a first region and a second region;
a first gate-all-around (GAA) device located in the first region, the first GAA device including:
a plurality of first nanosheets vertically stacked above the substrate,
a first work function (WF) layer of a first conductive type wrapping each of the first nanosheets, and
a first WF isolation layer disposed over the first WF layer and wrapping each of the first nanosheets; and
a second GAA device located in the second region, the second GAA device including:
a plurality of second nanosheets vertically stacked above the substrate,
a second WF layer of a second conductive type wrapping each of the second nanosheets, wherein the first and second conductive types are opposite, and
a second WF isolation layer disposed over the second WF layer and wrapping each of the second nanosheets, wherein the first WF isolation layer is a semiconductive layer and the second WF isolation layer is a metal nitride layer.
10. The semiconductor device of claim 9 , wherein the first WF layer has a substantially uniform thickness surrounding each of the first nanosheets, and the second WF layer has a substantially uniform thickness surrounding each of the second nanosheets.
11. The semiconductor device of claim 9 , wherein the second WF layer is also disposed over the first WF isolation layer in the first region.
12. The semiconductor device of claim 11 , wherein the second WF isolation layer is also disposed over the second WF layer in the first region.
13. A method of manufacturing a semiconductor device, comprising:
forming a structure having a plurality of nanosheets vertically stacked above a substrate;
depositing a gate dielectric layer surrounding each of the nanosheets;
depositing a metal layer over the gate dielectric layer and surrounding each of the nanosheets;
depositing a semiconductive layer over the metal layer and surrounding each of the nanosheets, wherein the semiconductive layer fills gaps between neighboring nanosheets;
depositing a metal nitride layer surrounding the semiconductive layer but not in the gaps; and
forming a metal fill layer over the metal nitride layer and surrounding the nanosheets but not in the gaps.
14. The method of claim 13 , wherein the semiconductive layer is a silicon layer.
15. The method of claim 13 , wherein the metal layer is an n-type work function layer.
16. The method of claim 13 , further comprising:
prior to the forming of the metal fill layer, depositing a metal alloy nitride layer surrounding the metal nitride layer but not in the gaps.
17. The method of claim 1 , wherein the second WF isolation layer is a titanium aluminum nitride layer.
18. The method of claim 1 , wherein the first WF isolation layer is thicker than the second WF isolation layer.
19. The method of claim 1 , wherein the first WF isolation layer is thinner than the second WF isolation layer.
20. The method of claim 9 , wherein the semiconductive layer includes amorphous silicon or polysilicon.