Granted Patent B2

US 12,324,358 · App. 17/539,316 · Granted Jun 3, 2025

Inventors: Ashim Dutta (Clifton Park, NY); Lili Cheng (Rexford, NY); Chih-Chao Yang (Glenmont, NY)

Assignee: International Business Machines Corporation

H10N50/80H10B61/00H10N50/01

Abstract

Claims (22)

1. A semiconductor structure comprising:

an embedded memory area interconnect structure and an embedded non-memory area interconnect structure, the memory area interconnect structure comprising metal interconnects formed in a substrate;

a first top contact on a metal interconnect of the non-memory area interconnect structure;

a bottom metal contact in a trench of dielectric material on a first metal interconnect of the memory area interconnect structure, a bottom surface of the bottom metal contact lower than a bottom surface of the first top contact;

a memory element stack pillar on the bottom metal contact;

a pillar encapsulation layer present on sidewalls of the memory element stack pillar, wherein:

the pillar encapsulation layer comprises a dielectric material; and

a bottom surface of the pillar encapsulation layer of the non-memory area interconnect structure is higher than a bottom surface of the pillar encapsulation layer of the memory area interconnect structure; and

a metal cap directly contacting a top surface of a second metal interconnect of the memory area interconnect structure, wherein:

the top surface of the metal cap is lower than a top surface of the bottom metal contact; and

the top surface of the metal cap directly contacts the bottom surface of the pillar encapsulation layer of the memory area interconnect structure.

2. The semiconductor structure of claim 1 , further comprising multiple layers of dielectric material on a sidewall of the first top contact.

3. The semiconductor structure of claim 1 , wherein the memory element stack pillar comprises a magnetic tunnel junction (MTJ) stack.

4. The semiconductor structure of claim 1 , wherein a width of the metal cap is greater than a combined width of: (i) the second metal contact interconnect of the memory area interconnect structure and (ii) a barrier layer present on sidewalls of the second metal interconnect of the memory area interconnect structure.

5. The semiconductor structure of claim 1 , further comprising a barrier layer present on each sidewall and bottom surface of: the metal interconnect of the non-memory area interconnect structure, the bottom metal contact, the first metal interconnect of the memory area interconnect structure, and the first top contact.

6. The semiconductor structure of claim 5 , wherein the barrier layer is of a material selected from the group consisting of: WN and WCN.

7. The semiconductor structure of claim 1 , further comprising a second top contact over the memory element stack pillar.

8. The semiconductor structure of claim 7 , wherein a first distance between a top surface of the first top contact and the non-memory area interconnect structure is less than a second distance between a top surface of the second top contact and the memory area interconnect structure.

9. The semiconductor structure of claim 1 , wherein a width of the bottom metal contact is less than a width of the memory element stack pillar.

10. The semiconductor structure of claim 1 , further comprising an interlayer dielectric layer on exposed surfaces of the pillar encapsulation layer and sidewalls of the first top contact and a second top contact, the second top contact over the metal interconnect of the non-memory area interconnect structure, wherein the interlayer dielectric layer separates sidewalls of the first top contact and the second top contact.

11. The semiconductor structure of claim 3 , further comprising a top electrode on the MTJ stack.

12. The semiconductor structure of claim 3 , further comprising a bottom electrode between the MTJ stack and the bottom metal contact.

Assignments (1)

Continuity (1)

References Cited (20)