Photodetector comprising avalanche photodiodes and first region surrounding avalanche photodiodes
View Patent ↗A solid-state image sensor includes at least two or more APDs formed on a substrate. First regions are arranged outside the APDs as viewed in plane. Adjacent ones of the APDs and the first regions are separated from each other through a separation region. A first voltage V 21 is applied to a fourth semiconductor layer of the APD, and a second voltage V 22 is applied to a fifth semiconductor layer of the first region. The first voltage V 21 is higher than the second voltage V 22.
1. A photodetector comprising:
a semiconductor substrate including a first principal surface and a second principal surface that is opposite to the first principal surface in a thickness direction of the semiconductor substrate; and
at least two or more avalanche photodiodes (APDs) formed in the semiconductor substrate, wherein:
a first region is arranged outside the APDs as viewed in plane,
adjacent ones of the APDs and the first region are separated from each other through a separation region,
each APD includes a first semiconductor layer of a second conductive type included in the semiconductor substrate and a fourth semiconductor layer of a first conductive type contacting the first semiconductor layer,
the first region includes the first semiconductor layer and a fifth semiconductor layer of the first conductive type contacting the first semiconductor layer,
a first voltage V 21 is applied to the fourth semiconductor layer of each APD, and a second voltage V 22 is applied to the fifth semiconductor layer of the first region,
the first voltage V 21 is higher than the second voltage V 22 ,
a third voltage Vrev is applied to the second principal surface,
the first voltage V 21 , the second voltage V 22 , and the third voltage Vrev are controlled so that a difference between a first reverse bias V 1 to be applied to each APD and a second reverse bias V 2 to be applied to the first region is smaller than a difference in potential between the separation region and the first region, and
following relationships are satisfied:
| V 1|= V 21 +|V rev| (1), and
| V 2|= V 22 +|V rev| (2).
2. The photodetector of claim 1 , wherein
the separation region is depleted at least part of a first principal surface of the semiconductor substrate.
3. The photodetector of claim 2 , wherein
in the separation region, no contact connected to the separation region is arranged, and no trench extending inwardly from a surface of the separation region is formed.
4. The photodetector of claim 1 , wherein
the first voltage V 21 and the second voltage V 22 are controlled so that the difference between the first reverse bias V 1 and the second reverse bias UV 2 is greater than an excess bias voltage as a difference between an absolute value of a voltage to be applied upon operation of each APD and an absolute value of a breakdown voltage of each APD.
5. The photodetector of claim 1 , wherein
an absolute value of a breakdown voltage of the first region is greater than the absolute value of the breakdown voltage of each APD.
6. The photodetector of claim 5 , wherein
a PN junction boundary in the first region is positioned inside the semiconductor substrate with respect to a PN junction boundary in each APD.
7. The photodetector of claim 5 , wherein
a difference between the absolute value of the breakdown voltage of the first region and the absolute value of the breakdown voltage of each APD is greater than the excess bias voltage as the difference between the absolute value of the voltage to be applied upon operation of each APD and the absolute value of the breakdown voltage of each APD.
8. The photodetector of claim 1 , further comprising:
a pixel circuit region,
wherein the pixel circuit region has a circuit well, and
an absolute value of a breakdown voltage between the circuit well and the first semiconductor layer is greater than the absolute value of the breakdown voltage of each APD.
9. The photodetector of claim 8 , wherein
the breakdown voltage of the first region is equal to the breakdown voltage between the circuit well and the first semiconductor layer.
10. The photodetector of claim 8 , wherein:
the circuit well includes a seventh semiconductor layer of the first conductive type formed on the semiconductor substrate and an eighth semiconductor layer of the first conductive type contacting the seventh semiconductor layer,
an impurity concentration of the fifth semiconductor layer is equal to an impurity concentration of the seventh semiconductor layer, and
a depth of the fifth semiconductor layer and a depth of the seventh semiconductor layer are equal to each other with reference to the first principal surface of the semiconductor substrate.
11. The photodetector of claim 1 , wherein
the first region is, as viewed in plane, formed in a frame shape surrounding one or more APDs.
12. The photodetector of claim 1 , wherein
the first region further has a tenth semiconductor layer of the first conductive type extending to project to a side opposite to an adjacent one of the APDs in a vicinity of a junction surface between the first region and the first semiconductor layer.
13. The photodetector of claim 1 , further comprising:
an electric field relaxing region outside the first region,
wherein an impurity concentration of the electric field relaxing region is lower than an impurity concentration of the first semiconductor layer, and
no silicide is formed on a surface of the electric field relaxing region.
14. The photodetector of claim 13 , wherein
a large portion of the electric field relaxing region is covered with a shallow trench isolation (STI).
15. The photodetector of claim 1 , wherein
the APDs are operated in a Geiger multiplication mode, and
each APD is at least temporarily connected only to a capacitor upon photodetection.
16. The photodetector of claim 15 , wherein
the first region is connected to a resistor in series.