Semiconductor device having power rail with non-linear edge
A semiconductor device includes a plurality of active regions extending in a first direction. The semiconductor device further includes a gate electrode over the plurality of active regions, wherein the gate electrode extends in a second direction perpendicular to the first direction. The semiconductor device further includes a power rail extending in the first direction. The power rail includes a first power rail portion adjacent to the first boundary, wherein the first power rail portion has a first inner edge, and a second power rail portion adjacent to the second boundary, wherein the second power rail portion has a second inner edge, and the first inner edge is offset from the second inner edge in the second direction.
1. A semiconductor device, comprising:
a plurality of active regions extending in a first direction;
a gate electrode over the plurality of active regions, wherein the gate electrode extends in a second direction perpendicular to the first direction;
a power rail extending in the first direction, wherein the power rail comprises:
a first power rail portion adjacent to the first boundary, wherein the first power rail portion has a first inner edge, and
a second power rail portion adjacent to the second boundary, wherein the second power rail portion has a second inner edge, and the first inner edge is offset from the second inner edge in the second direction.
2. The semiconductor device of claim 1 , wherein a maximum width, in the second direction, of the first power rail portion is equal to a maximum width, in the second direction, of the second power rail portion.
3. The semiconductor device of claim 1 , wherein a maximum width, in the second direction, of the first power rail portion is greater than a maximum width, in the second direction, of the second power rail portion.
4. The semiconductor device of claim 1 , wherein the first power rail portion has a first outer edge, and the second power rail portion has a second outer edge aligned with the first outer edge.
5. The semiconductor device of claim 1 , wherein the first power rail portion has a first outer edge, and the second power rail portion has a second outer edge offset from the first outer edge in the second direction.
6. The semiconductor device of claim 1 , wherein each of the plurality of active regions comprises a fin.
7. The semiconductor device of claim 1 , further comprising:
a first contact line between the gate electrode and a first boundary of a cell;
a second contact line between the gate electrode and a second boundary of the cell, wherein the first contact line and the second contact line extend over at least one of the plurality of active regions.
8. A semiconductor device, comprising:
a plurality of active regions extending in a first direction;
a gate electrode over the plurality of active regions, wherein the gate electrode extends in a second direction perpendicular to the first direction;
a power rail extending in the first direction, wherein the power rail comprises:
a first power rail portion adjacent to the first boundary, wherein the first power rail portion has a first outer edge, and
a second power rail portion adjacent to the second boundary, wherein the second power rail portion has a second outer edge, and the first outer edge is offset from the second outer edge in the second direction.
9. The semiconductor device of claim 8 , further comprising a conductive line extending in the first direction, wherein the conductive line is over the gate electrode.
10. The semiconductor device of claim 9 , wherein the first outer edge is closer to the conductive line than the second outer edge.
11. The semiconductor device of claim 8 , wherein a width of the first power rail portion adjacent to the first boundary is equal to a width of the second power rail portion adjacent to the second boundary.
12. The semiconductor device of claim 8 , further comprising a second power rail on an opposite side of the semiconductor device from the power rail.
13. The semiconductor device of claim 12 , wherein the second power rail comprises:
a third power rail portion adjacent to the first boundary, wherein the third power rail portion has a third outer edge, and
a fourth power rail portion adjacent to the second boundary, wherein the fourth power rail portion has a fourth outer edge, and the third outer edge is offset from the fourth outer edge in the second direction.
14. The semiconductor device of claim 8 , wherein a width of the power rail at a junction of the first power rail portion and the second power rail portion is less than a width of the first power rail portion adjacent to the first boundary.
15. A semiconductor device, comprising:
a plurality of active regions extending in a first direction;
a gate electrode over the plurality of active regions, wherein the gate electrode extends in a second direction perpendicular to the first direction;
a first power rail extending in the first direction, wherein the first power rail comprises:
a first power rail portion adjacent to the first boundary, wherein the first power rail portion has a first width,
a second power rail portion adjacent to the second boundary, wherein the second power rail portion has the first width, and
the first power rail has a second width at an intersection of the first power rail portion and the second power rail portion.
16. The semiconductor device of claim 15 , further comprising a second power rail on an opposite side of the semiconductor device from the first power rail.
17. The semiconductor device of claim 16 , wherein the second power rail comprises a third power rail portion adjacent to the first boundary, and the third power rail portion has the first width.
18. The semiconductor device of claim 15 , further comprising a conductive line extending in the first direction.
19. The semiconductor device of claim 18 , wherein the first power rail portion has a first inner edge, the second power rail portion has a second inner edge, and the first inner edge is closer to the conductive line than the second inner edge.
20. The semiconductor device of claim 18 , wherein the first power rail portion has a first outer edge, the second power rail portion has a second outer edge, and the first outer edge is farther from the conductive line than the second outer edge.