Lateral bipolar transistors
The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base having at least one sidewall with a gradient concentration of semiconductor material; an emitter on a first side of the extrinsic base; and a collector on a second side of the extrinsic base.
1. A structure comprising:
an extrinsic base comprising at least one sidewall comprising a gradient concentration of semiconductor material, the extrinsic base comprising a stack of semiconductor materials with a first semiconductor material, a second semiconductor material, a third semiconductor material, and a p-type semiconductor material comprising the at least one sidewall with the concentration of the semiconductor material and extending along an entire sidewall of the first semiconductor material and the second semiconductor material;
a spacer aligned with the at least one sidewall comprising the p-type semiconductor material, above the second semiconductor material and surrounding the third semiconductor material;
an emitter having a single top sloped surface and a thicker portion extending to and contacting the p-type semiconductor material;
a collector having a single top sloped surface and a thicker portion extending to and contacting the p-type semiconductor material; and
an emitter contact connecting to the single top sloped surface of the emitter; and
a collector contact connecting to the single top sloped surface of the collector.
2. The structure of claim 1 , wherein the emitter is on a first side of the extrinsic base and the single top sloped surface at least partially extends above a top surface of shallow trench isolation structures and to a top surface of the p-type semiconductor material.
3. The structure of claim 1 , wherein the emitter directly contacts the p-type semiconductor material with a thickest portion of the emitter extending to and directly contacting the p-type semiconductor material.
4. The structure of claim 1 , wherein the collector is on a second side of the extrinsic base and the single top sloped surface at least partially extends above the top surface of shallow trench isolation structures and to a top surface of the p-type semiconductor material.
5. The structure of claim 1 , wherein the collector directly contacts the p-type semiconductor material with a thickest portion of the collector extending to and directly contacting the p-type semiconductor material.
6. The structure of claim 1 , wherein the collector and emitter are bounded on a bottom surface by an underlying insulator layer, at a first side surface by the at least one sidewall having the gradient concentration of semiconductor material, at a second side surface by shallow trench isolation structures and on a top surface by interlevel dielectric material, the interlevel dielectric material also contacts the at least one sidewall and is above the extrinsic base.
7. The structure of claim 1 , wherein the emitter is a raised emitter and the collector is a raised collector, and the emitter and the collector cover the at least one sidewall with a first height and extend to shallow trench isolation structures with a second height that is lower than the first height.
8. The structure of claim 3 , wherein the emitter and the collector comprise Si material and the semiconductor material comprises SiGe material with a gradient concentration of Ge.
9. The structure of claim 8 , wherein the Si material comprises N+Si material and the SiGe material comprises P+ SiGe material.
10. The structure of claim 8 , wherein the gradient concentration of Ge ranges from about 0% to about 50%.
11. The structure of claim 1 , wherein the third semiconductor material of the extrinsic base comprises SiGe material surrounded by sidewall spacers.
12. The structure of claim 1 , wherein the extrinsic base comprises a core of SiGe material and Si material both of which include a recessed sidewall, and the gradient concentration of the semiconductor material is within the recessed sidewall.
13. A structure comprising:
an extrinsic base comprising a first semiconductor material, a second semiconductor material and a third semiconductor material;
a sidewall of epitaxial semiconductor material extending along an entire sidewall of the first semiconductor material and the second semiconductor material, and having a gradient concentration of semiconductor material, wherein the epitaxial semiconductor material comprises p-type material;
a spacer aligned with the sidewall comprising the epitaxial semiconductor material, above second semiconductor material and surrounding the third semiconductor material;
an emitter having a single top sloped surface and a thickest portion extending to and directly contacting the epitaxial semiconductor material;
a collector having a single top sloped surface and a thickest portion extending to and directly contacting the epitaxial semiconductor material;
an emitter contact connecting to the single top sloped surface of the emitter; and
a collector contact connecting to the single top sloped surface of the collector.
14. The structure of claim 13 , wherein the first semiconductor material comprises Si material and the second semiconductor material comprises SiGe material, wherein the raised emitter and the raised collector directly contact the sidewall.
15. The structure of claim 14 , wherein the gradient concentration of the second semiconductor material comprises a gradient concentration of Ge material.
16. The structure of claim 15 , wherein the gradient concentration of the Ge material comprises about 0% to 50%.
17. The structure of claim 15 , further comprising a recess in the first semiconductor material and the second semiconductor material, and the sidewall with the gradient concentration is within the recess.
18. The structure of claim 13 , wherein the emitter and the collector comprise a raised emitter and a raised collector directly contact the sidewall.
19. The structure of claim 13 , wherein the extrinsic base comprises opposing sidewalls with the gradient concentration of the semiconductor material.
20. A method comprising:
forming an extrinsic base comprising at least one sidewall comprising a gradient concentration of semiconductor material, the extrinsic base comprising a stack of semiconductor materials with a first semiconductor material, a second semiconductor material, a third semiconductor material, and a p-type semiconductor material comprising the at least one sidewall with the concentration of the semiconductor material and extending along an entire sidewall of the first semiconductor material and the second semiconductor material,
forming a spacer aligned with the at least one sidewall comprising the p-type semiconductor material, above the second semiconductor material and surrounding the third semiconductor material,
forming an emitter having a single top sloped surface and a thicker portion extending to and contacting the p-type semiconductor material,
forming a collector having a single top sloped surface and a thicker portion extending to and contacting the p-type semiconductor material; and
forming an emitter contact connecting to the single top sloped surface of the emitter; and
forming a collector contact connecting to the single top sloped surface of the collector.