Memory device and program operation thereof
A memory device is disclosed. The memory device may include a memory string and a peripheral circuit. The memory string may include a drain select gate (DSG) transistor, a plurality of memory cells, and a source select gate (SSG) transistor. The peripheral circuit may be coupled to the memory string and configured to, during a program operation on a select memory cell of the plurality of memory cells: after detecting an interrupt signal, perform a clean process that includes turning on at least one of the DSG transistor or the SSG transistor.
1. A memory device, comprising:
a memory string comprising a drain select gate (DSG) transistor, a plurality of memory cells, and a source select gate (SSG) transistor; and
a peripheral circuit coupled to the memory string and configured to, during a program operation on a select memory cell of the plurality of memory cells:
after detecting an interrupt signal, perform a clean process that comprises turning on at least one of the DSG transistor or the SSG transistor.
2. The memory device of claim 1 , wherein:
the program operation comprises a program phase where a program voltage is applied on a select word line coupled to the select memory cell; and
after detecting the interrupt signal during the program phase, the peripheral circuit is further configured to:
discharge the program voltage on the select word line; and
in the clean process, turn on the at least one of the DSG transistor or the SSG transistor, after or during discharging the program voltage.
3. The memory device of claim 2 , wherein the peripheral circuit is further configured to:
discharge the program voltage on the select word line to turn off the select memory cell; and
after turning off the select memory cell, in the clean process, apply an SSG voltage on an SSG line coupled to the SSG transistor to turn on the SSG transistor.
4. The memory device of claim 3 , wherein the peripheral circuit is further configured to, in the clean process:
while applying the SSG voltage on the SSG line, apply a pass voltage on the select word line to turn on the select memory cell.
5. The memory device of claim 2 , wherein the peripheral circuit is further configured to:
discharge the program voltage on the select word line to arrive at a pass voltage; and
while maintaining the pass voltage on the select word line, in the clean process, apply an SSG voltage on an SSG line coupled to the SSG transistor to turn on the SSG transistor.
6. The memory device of claim 1 , wherein the peripheral circuit is further configured to, in the clean process:
turn on the select memory cell; and
turn on an unselect memory cell of the plurality of memory cells, the unselect memory cell being between the select memory cell and the at least one of the DSG transistor or the SSG transistor.
7. The memory device of claim 1 , wherein:
the program operation comprises a verify phase where a verify voltage is applied on a select word line coupled to the select memory cell; and
the peripheral circuit is further configured to, in response to detecting the interrupt signal during the verify phase, in the clean process, raise a voltage on the select word line from the verify voltage to a pass voltage to turn on the select memory cell.
8. The memory device of claim 1 , wherein:
the interrupt signal is generated in response to one instance of detection of a power loss, detection of a power droop, a suspension instruction, and a reset instruction.
9. The memory device of claim 1 , wherein the peripheral circuit is further configured to:
after the clean process, discontinue the program operation.
10. The memory device of claim 9 , wherein:
the interrupt signal is detected in a cycle of the program operation; and
the peripheral circuit is further configured to in response to a receipt of a resume command, apply a verify voltage on a select word line coupled to the select memory cell, the verify voltage corresponding to the cycle.
11. The memory device of claim 1 , wherein the peripheral circuit is further configured to, in the clean process:
apply an SSG voltage on an SSG line coupled to the SSG transistor to turn on the SSG transistor;
apply a pass voltage on an unselect word line coupled to an unselect memory cell to turn on the unselect memory cell, the unselected memory cell being between the select memory cell and the SSG transistor; and
ground a source of the memory string.
12. The memory device of claim 1 , wherein:
the memory string is a first memory string, and the SSG transistor is a first SSG transistor coupled to a first SSG line;
the memory device further comprises a second memory string comprising a second SSG transistor coupled to a second SSG line; and
the peripheral circuit is further coupled to the second memory string and configured to, in the clean process:
apply an SSG voltage on the first SSG line coupled to the first SSG transistor; and
apply the SSG voltage on the second SSG line coupled to the second SSG transistor.
13. A memory system, comprising:
a memory device configured to store data and comprising:
a memory string comprising a drain select gate (DSG) transistor, a plurality of memory cells, and a source select gate (SSG) transistor; and
a peripheral circuit coupled to the memory string and configured to, during a program operation on a select memory cell of the plurality of memory cells:
after detecting an interrupt signal, perform a clean process that comprises turning on at least one of the DSG transistor or the SSG transistor; and
a memory controller coupled to the memory device and configured to transmit a program command to the peripheral circuit for the program operation.
14. The memory system of claim 13 , wherein:
the memory controller is further configured to transmit the interrupt signal to the peripheral circuit to initiate the clean process.
15. A method for operating a memory device comprising a memory string, the memory string comprising a drain select gate (DSG) transistor, a plurality of memory cells, and a source select gate (SSG) transistor, the method comprising:
initiating a program operation on a select memory cell of the plurality of memory cells; and
during the program operation, after detecting an interrupt signal, performing a clean process that comprises turning on at least one of the DSG transistor or the SSG transistor.
16. The method of claim 15 , wherein:
the program operation comprises a program phase where a program voltage is applied on a select word line coupled to the select memory cell; and
the method further comprises, after detecting the interrupt signal during the program phase:
discharging the program voltage on the select word line; and
turning on the at least one of the DSG transistor or SSG transistor, after or during discharging the program voltage, in the clean process.
17. The method of claim 15 , further comprising, in the clean process,
turning on the select memory cell; and
turning on an unselect memory cell of the plurality of memory cells, the unselect memory cell being between the select memory cell and the at least one of the DSG transistor or SSG transistor.
18. The method of claim 15 , wherein:
the program operation comprises a verify phase where a verify voltage is applied on a select word line coupled to the select memory cell; and
the method further comprises, in response to detecting the interrupt signal during the verify phase, in the clean process, increasing a voltage on the select word line from the verify voltage to a pass voltage to turn on the select memory cell.
19. The method of claim 15 , wherein:
the interrupt signal is generated in response to one instance of detection of a power loss, detection of a power droop, a suspension instruction, and a reset instruction.
20. The method of claim 15 , wherein:
the interrupt signal is detected in a cycle of the program operation; and
the method further comprises:
after the clean process, discontinuing the program operation; and
in response to a receipt of a resume command, applying a verify voltage on a select word line coupled to the select memory cell, the verify voltage corresponding to the cycle of the program operation.