Delamination control of dielectric layers of integrated circuit chips
A chip package and a method of fabricating the same are disclosed. The chip package includes a substrate with a first region, a second region surrounding the first region, and a third region surrounding the second region, a device layer disposed on the substrate, a via layer disposed on the device layer, an interconnect structure disposed on the via layer, and a stress buffer layer with tapered side profiles disposed on the interconnect structure. First and second portions of the via layer above the first and second regions include first and second set of vias. First, second, and third portions of the interconnect structure above the first, second, and third regions include conductive lines connected to the devices, a first set of dummy metal lines connected to the second set of vias, and a second set of dummy metal lines.
1. A structure, comprising:
a substrate with a first region, a second region surrounding the first region, and a third region surrounding the second region;
a device layer disposed on the substrate, wherein a portion of the device layer above the first region comprises devices;
a via layer disposed on the device layer, wherein a first portion of the via layer above the first region comprises a first set of vias and a second portion of the via layer above the second region comprises a second set of vias;
an interconnect structure disposed on the via layer, wherein a first portion of the interconnect structure above the first region comprises conductive lines connected to the devices, a second portion of the interconnect structure above the second region comprises a first set of dummy metal lines connected to the second set of vias, and a third portion of the interconnect structure above the third region comprises a second set of dummy metal lines; and
a stress buffer layer with tapered side profiles disposed on the first and second portions of the interconnect structure.
2. The structure of claim 1 , where a distance between adjacent dummy metal lines in the second set of dummy metal lines is about 40 nm to about 160 nm.
3. The structure of claim 1 , wherein the second set of dummy metal lines covers about 30% to about 50% of a total surface area of the third region.
4. The structure of claim 1 , wherein a width of each via in the second set of vias is about 20 nm to about 60 nm.
5. The structure of claim 1 , wherein a total number of vias in the second set of vias is greater than 10.
6. The structure of claim 1 , wherein the first set of vias are disposed on and in physical contact with contact structures of the device layer.
7. The structure of claim 1 , wherein the second set of vias are disposed on and in physical contact with a dielectric layer.
8. The structure of claim 1 , wherein at least one dummy metal line in the first set of dummy metal lines is in physical contact with a plurality of vias in the second set of vias.
9. The structure of claim 1 , wherein the first region is a device region, the second region is a seal-ring region, and the third region is a scribe lane region.
10. The structure of claim 1 , wherein sidewalls of the stress buffer layer form angles greater than about 50 degrees and less than about 90 degrees with a horizontal axis.
11. A structure, comprising:
a substrate with an active region, a first dummy region surrounding the active region, and a second dummy region surrounding the first dummy region;
a device layer disposed on the substrate, wherein a portion of the device layer above the active region comprises devices disposed on the substrate and contact structures disposed on the devices;
a via layer disposed on the device layer, wherein a first portion of the via layer above the active region comprises a first set of vias and a second portion of the via layer in the first dummy region comprises a second set of vias;
an interconnect structure disposed on the via layer, wherein:
a first portion of the interconnect structure above the active region comprises a conductive structure connected to the contact structures through the first set of vias,
a second portion of the interconnect structure above the first dummy region comprises a metal structure connected to the second set of vias, and
a third portion of the interconnect structure above the second dummy region comprises an array of conductive stacks that are arranged in an L-shaped pattern at a corner of the first dummy region; and
a redistribution layer disposed on the interconnect structure.
12. The structure of claim 11 , where a distance between adjacent conductive stacks in the array of conductive stacks is about 40 nm to about 160 nm.
13. The structure of claim 11 , wherein the array of conductive stacks covers about 30% to about 50% of a total surface area of the second dummy region.
14. The structure of claim 11 , wherein a width of each via in the second set of vias is about 20 nm to about 60 nm.
15. The structure of claim 11 , wherein a total number of vias in the second set of vias is greater than 10.
16. The structure of claim 11 , further comprising a stress buffer layer with tapered side profiles disposed on the first and second portions of the interconnect structure and not on the third portion of the interconnect structure, wherein sidewalls of the stress buffer layer form angles greater than about 50 degrees and less than about 90 degrees with a horizontal axis.
17. A structure, comprising:
a substrate with an active region, a first dummy region surrounding the active region, and a second dummy region surrounding the first dummy region;
a device layer comprising devices disposed in the active region of the substrate;
a via layer comprising vias disposed on the device layer; and
an interconnect structure, comprising:
a first interconnect portion with conductive lines in the active region and in contact with the devices in the device layer;
a second interconnect portion with a first set of dummy metal lines in the first dummy region and in contact with the vias in the via layer; and
a third interconnect portion with a second set of dummy metal lines in the second dummy region and arranged in an L-shaped pattern at a corner of the first dummy region.
18. The structure of claim 17 , wherein the second set of dummy metal lines covers about 30% to about 50% of a total surface area of the second dummy region.
19. The structure of claim 17 , wherein a first set of the vias are disposed on and in contact with the device layer; and
wherein a second set of the vias are disposed on and in contact with a dielectric layer.
20. The structure of claim 17 , further comprising an insulating layer disposed on the interconnect structure and comprising an oxide layer and a nitride layer.