Semiconductor memory devices with dielectric fin structures
View Patent ↗A semiconductor device includes a plurality of first nanostructures extending along a first lateral direction. The semiconductor device includes a first epitaxial structure and second epitaxial structure respectively coupled to ends of each of the plurality of first nanostructures along the first lateral direction. The semiconductor device includes a dielectric fin structure disposed immediately next to a sidewall of each of the plurality of first nanostructures facing a second lateral direction perpendicular to the first lateral direction. The semiconductor device includes a first gate structure wrapping around each of the plurality of first nanostructures except for the sidewalls of the first nanostructures. The semiconductor device includes a metal structure disposed above the first gate structure and coupled to one of the first or second epitaxial structure.
1. A semiconductor device, comprising:
a dielectric fin structure extending along a first lateral direction;
a plurality of first nanostructures extending along the first lateral direction, wherein each of the plurality of first nanostructures has a first sidewall in direct contact with the dielectric fin structure;
a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewall;
a plurality of second nanostructures extending along the first lateral direction, wherein each of the plurality of second nanostructures has a second sidewall in direct contact with the dielectric fin structure; and
a second gate structure wrapping around each of the plurality of second nanostructures except for the second sidewall.
2. The semiconductor device of claim 1 , wherein the first sidewall and the second sidewall face each other along a second lateral direction perpendicular to the first lateral direction.
3. The semiconductor device of claim 1 , further comprising a first epitaxial structure and second epitaxial structure respectively coupled to ends of each of the plurality of first nanostructures along the first lateral direction.
4. The semiconductor device of claim 3 , further comprising a metal structure disposed above the first and second gate structures, and coupled to one of the first or second epitaxial structure.
5. The semiconductor device of claim 4 , wherein the metal structure extends along the first lateral direction.
6. The semiconductor device of claim 4 , wherein the plurality of first nanostructures, the first and second epitaxial structures, and the first gate structure collectively form a first transistor, and the metal structure forms a resistor.
7. The semiconductor device of claim 6 , wherein the first transistor and resistor are coupled to each other in series.
8. The semiconductor device of claim 7 , wherein the serially coupled first transistor and resistor collectively function as a first one-time-programmable memory.
9. The semiconductor device of claim 6 , further comprising a third epitaxial structure and fourth epitaxial structure respectively coupled to ends of each of the plurality of second nanostructures along the first lateral direction.
10. The semiconductor device of claim 9 , wherein the plurality of second nanostructures, the third and fourth epitaxial structures, and the second gate structure collectively form a second transistor, and wherein the second transistor is electrically coupled to the first transistor in parallel.
11. A semiconductor device, comprising:
a first dielectric fin structure extending along a first lateral direction;
a second dielectric fin structure also extending along the first lateral direction;
a plurality of first nanostructures extending along the first lateral direction, wherein each of the plurality of first nanostructures has a first sidewall in direct contact with the first dielectric fin structure;
a plurality of second nanostructures extending along the first lateral direction, wherein each of the plurality of second nanostructures has a second sidewall in direct contact with the first dielectric fin structure;
a plurality of third nanostructures extending along the first lateral direction, wherein each of the plurality of third nanostructures has a third sidewall in direct contact with the second dielectric fin structure;
a plurality of fourth nanostructures extending along the first lateral direction, wherein each of the plurality of fourth nanostructures has a fourth sidewall in direct contact with the second dielectric fin structure;
a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewall;
a second gate structure wrapping around each of the plurality of second nanostructures except for the second sidewall and each of the plurality of third nanostructures except for the third sidewall; and
a third gate structure wrapping around each of the plurality of fourth nanostructures except for the fourth sidewall.
12. The semiconductor device of claim 11 , wherein the first sidewall and the second sidewall face each other along a second lateral direction perpendicular to the first lateral direction, and the third sidewall and the fourth sidewall face each other along the second lateral direction.
13. The semiconductor device of claim 11 , wherein the first to third gate structures each extend along a second lateral direction perpendicular to the first lateral direction.
14. The semiconductor device of claim 13 , wherein the first gate structure is separated from the second gate structure with the first dielectric fin structure, and the third gate structure is separated from the second gate structure with the second dielectric fin structure.
15. The semiconductor device of claim 11 , further comprising:
a first epitaxial structure and second epitaxial structure respectively coupled to ends of each of the plurality of first nanostructures along the first lateral direction;
a third epitaxial structure and fourth epitaxial structure respectively coupled to ends of each of the plurality of second nanostructures along the first lateral direction;
a fifth epitaxial structure and sixth epitaxial structure respectively coupled to ends of each of the plurality of third nanostructures along the first lateral direction; and
a seventh epitaxial structure and eighth epitaxial structure respectively coupled to ends of each of the plurality of fourth nanostructures along the first lateral direction.
16. The semiconductor device of claim 15 , wherein
the plurality of first nanostructures, the first and second epitaxial structures, and the first gate structure collectively form a first transistor;
the plurality of second nanostructures, the third and fourth epitaxial structures, and the second gate structure collectively form a first transistor;
the plurality of third nanostructures, the fifth and sixth epitaxial structures, and the second gate structure collectively form a third transistor; and
the plurality of fourth nanostructures, the seventh and eighth epitaxial structures, and the third gate structure collectively form a fourth transistor.
17. The semiconductor device of claim 16 , wherein the first to fourth transistors are connected to each other in parallel.
18. The semiconductor device of claim 17 , further comprising:
a resistor formed of at least one metal structure disposed above the first to third gate structures;
wherein the at least one metal structure has one end coupled to one of the first or second epitaxial structure, one of the third or fourth epitaxial structure, one of the fifth or sixth epitaxial structure, and one of the seventh or eighth epitaxial structure.
19. A semiconductor device, comprising:
a dielectric fin structure extending along a first lateral direction;
a plurality of first nanostructures extending along the first lateral direction, wherein each of the plurality of first nanostructures has a first sidewall in direct contact with the dielectric fin structure;
a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewall;
a plurality of second nanostructures extending along the first lateral direction, wherein each of the plurality of second nanostructures has a second sidewall in direct contact with the dielectric fin structure;
a second gate structure wrapping around each of the plurality of second nanostructures except for the second sidewall;
a first epitaxial structure and second epitaxial structure respectively coupled to ends of each of the plurality of first nanostructures along the first lateral direction;
a third epitaxial structure and fourth epitaxial structure respectively coupled to ends of each of the plurality of second nanostructures along the first lateral direction; and
a metal structure disposed above the first and second gate structures, wherein the metal structure has one end coupled to one of the first or second epitaxial structure, and one of the third or fourth epitaxial structure.
20. The semiconductor device of claim 19 , wherein
the plurality of first nanostructures, the first and second epitaxial structures, and the first gate structure collectively form a first transistor;
the plurality of second nanostructures, the third and fourth epitaxial structures, and the second gate structure collectively form a second transistor; and
the metal structure forms a resistor;
wherein the first transistor and the second transistor are connected to each in parallel, and each of the first transistor and the second transistor is connected to the resistor in series.