Integrated circuit structures having cut metal gates with dielectric spacer fill
An integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is laterally around the first gate stack and has a portion along an end of the first gate stack and in the gap. A second dielectric gate spacer is laterally around the second gate stack and has a portion along an end of the second gate stack and in the gap. The portion of the second dielectric gate spacer is laterally merged with the portion of the first dielectric gate spacer in the gap.
1. An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires;
a second vertical arrangement of horizontal nanowires;
a first gate stack over the first vertical arrangement of horizontal nanowires;
a second gate stack over the second vertical arrangement of horizontal nanowires, an end of the second gate stack spaced apart from an end of the first gate stack by a gap;
a first dielectric gate spacer laterally around the first gate stack and having a first portion along an end of the first gate stack and in the gap, and a second portion along sidewalls of the first gate stack, the second portion continuous with the first portion; and
a second dielectric gate spacer laterally around the second gate stack and having a first portion along an end of the second gate stack and in the gap, and a second portion along sidewalls of the second gate stack, the second portion continuous with the first portion, wherein the first portion of the second dielectric gate spacer is laterally merged with the first portion of the first dielectric gate spacer in the gap.
2. The integrated circuit structure of claim 1 , further comprising:
a first conductive contact along a first side of the first and second gate stacks; and
a second conductive contact along a second side of the first and second gate stacks, wherein the portion of the second dielectric gate spacer and the portion of the first dielectric gate spacer electrically isolate the second conductive contact from the first conductive contact.
3. The integrated circuit structure of claim 1 , further comprising:
a first pair of epitaxial source or drain structures at first and second ends of the first vertical arrangement of horizontal nanowires; and
a second pair of epitaxial source or drain structures at first and second ends of the second vertical arrangement of horizontal nanowires.
4. The integrated circuit structure of claim 3 , wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of non-discrete epitaxial source or drain structures.
5. An integrated circuit structure, comprising:
a first fin;
a second fin;
a first gate stack over the first fin;
a second gate stack over the second fin, an end of the second gate stack spaced apart from an end of the first gate stack by a gap;
a first dielectric gate spacer laterally around the first gate stack and having a first portion along an end of the first gate stack and in the gap, and a second portion along sidewalls of the first gate stack, the second portion continuous with the first portion; and
a second dielectric gate spacer laterally around the second gate stack and having a first portion along an end of the second gate stack and in the gap, and a second portion along sidewalls of the second gate stack, the second portion continuous with the first portion, wherein the first portion of the second dielectric gate spacer is laterally merged with the first portion of the first dielectric gate spacer in the gap.
6. The integrated circuit structure of claim 5 , further comprising:
a first conductive contact along a first side of the first and second gate stacks; and
a second conductive contact along a second side of the first and second gate stacks, wherein the portion of the second dielectric gate spacer and the portion of the first dielectric gate spacer electrically isolate the second conductive contact from the first conductive contact.
7. The integrated circuit structure of claim 5 , further comprising:
a first pair of epitaxial source or drain structures at first and second ends of the first fin; and
a second pair of epitaxial source or drain structures at first and second ends of the second fin.
8. The integrated circuit structure of claim 7 , wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of non-discrete epitaxial source or drain structures.
9. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires;
a second vertical arrangement of horizontal nanowires;
a first gate stack over the first vertical arrangement of horizontal nanowires;
a second gate stack over the second vertical arrangement of horizontal nanowires, an end of the second gate stack spaced apart from an end of the first gate stack by a gap;
a first dielectric gate spacer laterally around the first gate stack and having a first portion along an end of the first gate stack and in the gap, and a second portion along sidewalls of the first gate stack, the second portion continuous with the first portion; and
a second dielectric gate spacer laterally around the second gate stack and having a first portion along an end of the second gate stack and in the gap, and a second portion along sidewalls of the second gate stack, the second portion continuous with the first portion, wherein the first portion of the second dielectric gate spacer is laterally merged with the first portion of the first dielectric gate spacer in the gap.
10. The computing device of claim 9 , further comprising:
a memory coupled to the board.
11. The computing device of claim 9 , further comprising:
a communication chip coupled to the board.
12. The computing device of claim 11 , wherein the component is a packaged integrated circuit die.
13. The computing device of claim 9 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
14. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first fin;
a second fin;
a first gate stack over the first fin;
a second gate stack over the second fin, an end of the second gate stack spaced apart from an end of the first gate stack by a gap;
a first dielectric gate spacer laterally around the first gate stack and having a first portion along an end of the first gate stack and in the gap, and a second portion along sidewalls of the first gate stack, the second portion continuous with the first portion; and
a second dielectric gate spacer laterally around the second gate stack and having a first portion along an end of the second gate stack and in the gap, and a second portion along sidewalls of the second gate stack, the second portion continuous with the first portion, wherein the first portion of the second dielectric gate spacer is laterally merged with the first portion of the first dielectric gate spacer in the gap.
15. The computing device of claim 14 , further comprising:
a memory coupled to the board.
16. The computing device of claim 14 , further comprising:
a communication chip coupled to the board.
17. The computing device of claim 14 , wherein the component is a packaged integrated circuit die.
18. The computing device of claim 14 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.