Semiconductor package with balanced wiring structure
Provided is a semiconductor package having improved signal integrity (SI) and a chip stack structure of a plurality of semiconductor chips. The semiconductor package includes a package substrate, a chip stack structure on the package substrate and including at least two semiconductor chips, and an external connection terminal on a lower surface of the package substrate. A first semiconductor chip arranged uppermost in the chip stack structure is connected to a first bonding pad of the package substrate through a first wire. A second semiconductor chip arranged under the first semiconductor chip in the chip stack structure is connected to a second bonding pad of the package substrate through a second wire. When the first bonding pad is farther from the external connection terminal than the second bonding pad, the external connection terminal is connected to the first bonding pad through a wiring line of the package substrate.
1. A semiconductor package comprising:
a package substrate;
a chip stack structure on an upper surface of the package substrate, the chip stack structure including at least two semiconductor chips; and
an external connection terminal on a lower surface of the package substrate,
wherein the at least two semiconductor chips include a first semiconductor chip and a second semiconductor chip,
the first semiconductor chip is an uppermost one from among the at least two semiconductor chips and is connected to a first bonding pad of the package substrate through a first wire,
the second semiconductor chip is under the first semiconductor chip from among the at least two semiconductor chips and is connected to a second bonding pad of the package substrate through a second wire,
the first bonding pad is connected to the second bonding pad through an upper wiring line on the package substrate,
the upper wiring line horizontally extends on the package substrate and includes a first portion and a second portion, the first portion extending from the first bonding pad in a direction away from the at least two semiconductor chips, the second portion horizontally extending between the first bonding pad and the second bonding pad,
the first bonding pad is farther from the external connection terminal than the second bonding pad,
the external connection terminal is connected to the first bonding pad through a wiring line of the package substrate and is connected to the second bonding pad through the wiring line, the first bonding pad, and the upper wiring line,
the first wire, the first bonding pad, the first portion of the upper wiring line, and the wiring line are sequentially connected, and
a length of the second portion of the upper wiring line is proportional to a difference between a length of the first wire and a length of the second wire.
2. The semiconductor package of claim 1 , wherein
when viewed from the external connection terminal, a sum of a length of the second wire and a length of the upper wiring line between the second bonding pad and the first bonding pad is equal or comparable to a length of the first wire.
3. The semiconductor package of claim 2 , wherein
at least one of the at least two semiconductor chips includes a chip pad, a connection pad connected to a wire that is connected to a bonding pad of the package substrate, and a rewiring line connecting the chip pad to the connection pad.
4. The semiconductor package of claim 1 , wherein
the chip stack structure comprises four semiconductor chips,
the second semiconductor chip is a lowermost semiconductor chip,
a third semiconductor chip is on the second semiconductor chip and is connected to a third bonding pad of the package substrate through a third wire,
a fourth semiconductor chip is on the third semiconductor chip and is connected to a fourth bonding pad of the package substrate through a fourth wire,
lengths of first to fourth wires are shorter in an order of the first wire, the fourth wire, the third wire, and the second wire,
first to fourth bonding pads are farther from the chip stack structure in an order of the second bonding pad, the third bonding pad, the fourth bonding pad, and the first bonding pad,
the third and fourth bonding pads are connected to the first bonding pad through an upper wiring line, and
each of a sum of a length of the third wire and a length of the upper wiring line between the first bonding pad and the third bonding pad and a sum of a length of the fourth wire and a length of the upper wiring line between the first bonding pad and the fourth bonding pad is equal or comparable to a length of the first wire.
5. The semiconductor package of claim 1 , wherein
the at least two semiconductor chips have a same size, and
the chip stack structure has one of
a first structure in which the at least two semiconductor chips are stacked so that sides of the at least two semiconductor chips coincide with one another,
a second structure in which the at least two semiconductor chips are stacked so that the sides of the at least two semiconductor chips are stepped, or
a third structure in which the at least two semiconductor chips are stacked in zigzags.
6. The semiconductor package of claim 1 , wherein
at least one of the at least two semiconductor chips has a size different from sizes of the others of the at least two semiconductor chips, and
the chip stack structure has one of
a first structure in which the second semiconductor chip is on a bottom and the first semiconductor chip is on a top, the first semiconductor chip being larger than the second semiconductor chip, or
a second structure in which the second semiconductor chip is on a bottom and the first semiconductor chip is on a top, the second semiconductor chip being larger than the first semiconductor chip.
7. The semiconductor package of claim 1 , wherein
the first semiconductor chip is connected to the first bonding pad on each of opposite sides of the package substrate in a first direction through the first wire on a corresponding one of the opposite sides in the first direction,
the second semiconductor chip is connected to the second bonding pad on each of the opposite sides of the package substrate in the first direction through the second wire on a corresponding one of the opposite sides in the first direction,
the second bonding pad is connected to the first bonding pad through the upper wiring line on the package substrate, and
the external connection terminal is on an opposite side to the first bonding pad with respect to the chip stack structure.
8. The semiconductor package of claim 1 , further comprising:
at least one internal semiconductor chip apart from the chip stack structure and mounted on the package substrate,
wherein the internal semiconductor chip is connected to a signal pad of the package substrate through a wire or a bump,
the first bonding pad is farther from the signal pad than the second bonding pad, and
the signal pad is connected to the first bonding pad through a wiring line of the package substrate.
9. The semiconductor package of claim 1 , wherein
the wiring line connects the first bonding pad to an external pad having the external connection terminal thereon, and
the wiring line comprises an internal wiring line and a via contact.
10. The semiconductor package of claim 1 , wherein the external connection terminal and the first bonding pad connected thereto are configured to transmit a data signal or a command signal.
11. A semiconductor package comprising:
a package substrate;
a chip stack structure on the package substrate and including at least two semiconductor chips; and
at least one internal semiconductor chip apart from the chip stack structure and being on the package substrate,
wherein the at least two semiconductor chips include a first semiconductor chip and a second semiconductor chip,
the first semiconductor chip is an uppermost one from among the at least two semiconductor chips and is connected to a first bonding pad of the package substrate through a first wire,
the second semiconductor chip is under the first semiconductor chip from among the at least two semiconductor chips and is connected to a second bonding pad of the package substrate through a second wire,
the internal semiconductor chip is connected to a signal pad of the package substrate through a wire or a bump,
the first bonding pad is connected to the second bonding pad through an upper wiring line on the package substrate,
the upper wiring line horizontally extends on the package substrate and includes a first portion and a second portion, the first portion extending from the first bonding pad in a direction away from the at least two semiconductor chips, the second portion horizontally extending between the first bonding pad and the second bonding pad,
the first bonding pad is farther from the signal pad than the second bonding pad,
the signal pad is connected to the first bonding pad through a wiring line of the package substrate and is connected to the second bonding pad through the wiring line, the first bonding pad, and the upper wiring line,
the first wire, the first bonding pad, the first portion of the upper wiring line, and the wiring line are sequentially connected, and
a length of the second portion of the upper wiring line is proportional to a difference between a length of the first wire and a length of the second wire.
12. The semiconductor package of claim 11 , wherein
when viewed from the signal pad, a sum of a length of the second wire and a length of the upper wiring line between the first bonding pad and the second bonding pad is equal or comparable to a length of the first wire.
13. The semiconductor package of claim 12 , wherein
at least one of the at least two semiconductor chips includes a chip pad, a connection pad connected to a wire that is connected to a bonding pad of the package substrate, and a rewiring line connecting the chip pad to the connection pad.
14. The semiconductor package of claim 11 , further comprising:
an external connection terminal on a lower surface of the package substrate,
wherein the first bonding pad is farther from the external connection terminal than the second bonding pad,
the external connection terminal is connected to the first bonding pad through a wiring line of the package substrate,
the second bonding pad is connected to the first bonding pad through the upper wiring line on the package substrate, the upper wiring line being parallel to the package substrate, and
when viewed from the external connection terminal, a sum of a length of the second wire and a length of the upper wiring line between the first bonding pad and the second bonding pad is equal or comparable to a length of the first wire.
15. The semiconductor package of claim 11 , wherein the signal pad and the first bonding pad connected thereto are configured to transmit a data signal or a command signal.
16. A semiconductor package comprising:
a package substrate;
a chip stack structure on the package substrate and including at least two semiconductor chips;
at least one internal semiconductor chip apart from the chip stack structure and being on the package substrate; and
an external connection terminal on a lower surface of the package substrate,
wherein the at least two semiconductor chips include a first semiconductor chip and a second semiconductor chip,
the first semiconductor chip is an uppermost one from among the at least two semiconductor chips and is connected to a first bonding pad of the package substrate through a first wire,
the second semiconductor chip is under the first semiconductor chip from among the at least two semiconductor chips and is connected to a second bonding pad of the package substrate through a second wire,
the first bonding pad is connected to the second bonding pad through an upper wiring line on the package substrate,
the upper wiring line horizontally extends on the package substrate and includes a first portion and a second portion, the first portion extending from the first bonding pad in a direction away from the at least two semiconductor chips, the second portion horizontally extending between the first bonding pad and the second bonding pad,
the first bonding pad is farther from the external connection terminal than the second bonding pad,
the external connection terminal is connected to the first bonding pad through a wiring line of the package substrate and is connected to the second bonding pad through the wiring line, the first bonding pad, and the upper wiring line,
the first wire, the first bonding pad, the first portion of the upper wiring line, and the wiring line are sequentially connected, and
a length of the second portion of the upper wiring line is proportional to a difference between a length of the first wire and a length of the second wire.
17. The semiconductor package of claim 16 , wherein
when viewed from the external connection terminal, a sum of a length of the second wire and a length of the upper wiring line between the first bonding pad and the second bonding pad is equal or comparable to a length of the first wire.
18. The semiconductor package of claim 17 , wherein
at least one of the at least two semiconductor chips includes a chip pad, a connection pad connected to a wire that is connected to a bonding pad of the package substrate, and a rewiring line connecting the chip pad to the connection pad.
19. The semiconductor package of claim 16 , wherein
the at least one internal semiconductor chip is connected to a signal pad of the package substrate through a wire or a bump,
the first bonding pad is farther from the signal pad than the second bonding pad,
the signal pad is connected to the first bonding pad through a wiring line of the package substrate,
the second bonding pad is connected to the first bonding pad through the upper wiring line on the package substrate, and
when viewed from the signal pad, a sum of a length of the second wire and a length of the upper wiring line between the first bonding pad and the second bonding pad is equal or comparable to a length of the first wire.
20. The semiconductor package of claim 16 , wherein the chip stack structure has one of
a first structure in which the at least two semiconductor chips have a same size and are stacked so that sides of the at least two semiconductor chips coincide with one another,
a second structure in which the at least two semiconductor chips are stacked so that the sides of the at least two semiconductor chips are stepped,
a third structure in which the at least two semiconductor chips are stacked in zigzags,
a fourth structure in which the second semiconductor chip is on a bottom, and the first semiconductor chip is on a top, the first semiconductor chip being larger than the second semiconductor chip, or
a fifth structure in which the second semiconductor chip is on a bottom and the first semiconductor chip is on a top, the second semiconductor chip being larger than the first semiconductor chip.