Isolation structures of semiconductor devices
The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages.
1. A method, comprising:
forming a first gate-all-around field effect transistor (GAA FET), comprising:
forming a first GAA structure surrounding first nanostructured channel regions, and
forming, adjacent to the first GAA structure, a first doped epitaxial layer with dopants of a first type conductivity;
forming a second GAA FET, comprising:
forming a second GAA structure surrounding second nanostructured channel regions, and
forming, adjacent to the second GAA structure, a second doped epitaxial layer with dopants of the first type conductivity; and
forming an isolation structure, comprising:
forming, between the first and second GAA structures, a polysilicon gate structure with dopants of a second type conductivity.
2. The method of claim 1 , wherein forming the isolation structure further comprises:
forming a fin base on a substrate;
forming a stack of first and second nanostructured layers on the fin base; and
depositing a polysilicon layer on the stack of first and second nanostructured layers.
3. The method of claim 1 , wherein forming the isolation structure further comprises:
forming a stack of first and second nanostructured layers on a substrate;
patterning a polysilicon layer on the stack of first and second nanostructured layers to form the polysilicon gate structure; and
performing a doping process on the polysilicon gate structure.
4. The method of claim 1 , wherein forming the isolation structure further comprises doping the polysilicon gate structure with the dopants of the second type conductivity.
5. The method of claim 1 , wherein forming the isolation structure further comprises ion implanting the dopants of the second type conductivity into the polysilicon gate structure.
6. The method of claim 1 , wherein forming the first GAA FET comprises:
forming a fin base on a substrate;
forming a stack of first and second nanostructured layers on the fin base; and
forming the first doped epitaxial layer on the stack of first and second nanostructured layers.
7. The method of claim 1 , wherein forming the first GAA FET comprises:
forming a stack of first and second nanostructured layers on a substrate;
etching a portion of the first and second nanostructured layers to form an opening; and
forming the first doped epitaxial layer in the opening.
8. The method of claim 1 , wherein forming the first GAA FET comprises:
forming a stack of first and second nanostructured layers on a substrate;
forming a polysilicon structure on the stack of first and second nanostructured layers; and
replacing the polysilicon structure and portions of the second nanostructured layers under the polysilicon structure with the first GAA structure.
9. The method of claim 1 , wherein forming the first GAA FET comprises:
forming a stack of first and second nanostructured layers on a substrate;
patterning a polysilicon layer on the stack of first and second nanostructured layers to form a polysilicon structure and the polysilicon gate structure;
forming a masking layer on the polysilicon gate structure; and
replacing the polysilicon structure and portions of the second nanostructured layers under the polysilicon structure with the first GAA structure.
10. The method of claim 1 , wherein forming the first GAA structure and the second GAA structure are performed at a same time.
11. A method, comprising:
forming a stack of first and second nanostructured layers on a substrate;
forming first, second, and third polysilicon structures on the stack of first and second nanostructured layers;
forming doped regions with dopants of a first type conductivity between the first and second polysilicon structures and between the second and third polysilicon structures;
forming a masking layer on the first and third polysilicon structures;
doping the second polysilicon structure with dopants of a second type conductivity, wherein the second polysilicon structure is between the first and third polysilicon structures; and
replacing the first and third polysilicon structures with gate-all-around (GAA) structures.
12. The method of claim 11 , wherein doping the second polysilicon structure comprises ion implanting the dopants of the second type conductivity into the second polysilicon structure.
13. The method of claim 11 , wherein doping the second polysilicon structure comprises ion implanting boron, indium, gallium, phosphorus, or arsenic dopants into the second polysilicon structure.
14. The method of claim 11 , wherein doping the second polysilicon structure comprises performing an anneal process on the second polysilicon structure.
15. The method of claim 11 , wherein replacing the first and third polysilicon structures with GAA structures comprises etching portions of the second nanostructured layers under the first and third polysilicon structures.
16. The method of claim 11 , wherein replacing the first and third polysilicon structures with GAA structures comprises oxidizing surfaces of the first nanostructured layers under the first and third polysilicon structures.
17. A method, comprising:
forming a gate-all-around (GAA) structure surrounding nanostructured channel regions;
forming, adjacent to the GAA structure, a source/drain region with dopants of a first type conductivity; and
forming, adjacent to the source/drain region, a polysilicon gate structure with dopants of a second type conductivity opposite to the first type conductivity.
18. The method of claim 17 , wherein forming the polysilicon gate structure comprises ion implanting the dopants of the second type conductivity into the polysilicon gate structure.
19. The method of claim 17 , wherein forming the polysilicon gate structure comprises ion implanting boron, indium, gallium, phosphorus, or arsenic dopants into the polysilicon gate structure.
20. The method of claim 17 , forming the GAA structure comprises:
forming a stack of first and second nanostructured layers on a substrate;
forming a polysilicon structure on the stack of first and second nanostructured layers; and
replacing the polysilicon structure and portions of the second nanostructured layers under the polysilicon structure with the GAA structure.