Semiconductor devices and methods of manufacturing
View Patent ↗Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. Different thickness in an epi-growth scheme is adopted to create different sheet thicknesses within the same device channel regions for use in manufacturing vertically stacked nanostructure (e.g., nanosheet, nanowire, or the like) GAA devices. A GAA device may be formed with a vertical stack of nanostructures in a channel region with a topmost nanostructure of the vertical stack being thicker than the other nanostructures of the vertical stack. Furthermore, an LDD portion of the topmost nanostructure may be formed as the thickest of the nanostructures in the vertical stack.
1. A device comprising:
a vertical stack of nanostructures over a substrate, the vertical stack of nanostructures extending between a first source/drain region and a second source/drain region, wherein the first source/drain region and the second source/drain region extend into the substrate, wherein the vertical stack of nanostructures comprise:
a bottom nanostructure over the substrate;
a middle nanostructure over the bottom nanostructure; and
a top nanostructure over the middle nanostructure, wherein thicknesses of the vertical stack of nanostructures gradually increase from the bottom nanostructure to the top nanostructure;
a gate electrode surrounding the bottom nanostructure, the middle nanostructure, and the top nanostructure; and
a gate dielectric separating the gate electrode from the bottom nanostructure, the middle nanostructure, and the top nanostructure, wherein a first portion of the gate electrode and a second portion of the gate electrode are separated by the top nanostructure, wherein a first spacer extends along a first sidewall of the first portion of the gate electrode, wherein a second spacer extends along a first sidewall of the second portion of the gate electrode, and wherein the first spacer and the second spacer comprise different materials.
2. The device of claim 1 , wherein a first distance between the bottom nanostructure and the middle nanostructure is equal to a second distance between the middle nanostructure and the top nanostructure.
3. The device of claim 1 , wherein a first thickness of an end portion of the bottom nanostructure is greater than a second thickness of a central portion of the bottom nanostructure.
4. The device of claim 1 , wherein the top nanostructure has a first thickness and the middle nanostructure has a second thickness, a difference between the first thickness and the second thickness being between 0.5 nm and 3 nm.
5. The device of claim 1 , wherein the top nanostructure has a first thickness and the middle nanostructure has a second thickness, the first thickness is 1.05 times to 1.3 times as large as the second thickness.
6. A device comprising:
a stack of nanostructures over a substrate, wherein the stack of nanostructures comprise:
a first nanosheet of a first thickness, wherein the first nanosheet is spaced apart from the substrate by a first distance;
a second nanosheet of a second thickness, wherein the second thickness is greater than the first thickness, wherein the first nanosheet is disposed between the substrate and the second nanosheet, wherein the second nanosheet is spaced apart from the first nanosheet by a second distance, and wherein the second distance is equal to the first distance; and
a third nanosheet of a third thickness, wherein the third thickness is greater than the second thickness, wherein the second nanosheet is disposed between the first nanosheet and the third nanosheet, wherein the third nanosheet is spaced apart from the second nanosheet by a third distance, and wherein the third distance is equal to the second distance;
an electrode wrapping around the first nanosheet, the second nanosheet, and the third nanosheet; and
a first insulating layer disposed between the electrode and the first nanosheet, a second insulating layer disposed between the electrode and the second nanosheet, and a third insulating layer disposed between the electrode and the third nanosheet, wherein a first portion of the electrode and a second portion of the electrode are separated by the third nanosheet, wherein a first spacer extends along the first portion of the electrode, wherein a second spacer extends along the second portion of the electrode, and wherein the third insulating layer is disposed between the second portion of the electrode and the second spacer.
7. The device of claim 6 , wherein the first spacer comprises a different material from the second spacer.
8. The device of claim 6 , wherein a difference between the first thickness and the second thickness is in a range from 0.5 nm to 3 nm, and wherein a difference between the second thickness and the third thickness is in a range from 0.5 nm to 3 nm.
9. The device of claim 6 , wherein a ratio of the second thickness to the first thickness is in a range from 1.05 to 1.3, and wherein a ratio of the third thickness to the second thickness is in a range from 1.05 to 1.3.
10. The device of claim 6 , further comprising a gate end dielectric along a sidewall of the electrode.
11. The device of claim 6 , further comprising a gate via over the stack of nanostructures.
12. A semiconductor device comprising:
semiconductor nanostructures over a substrate, the semiconductor nanostructures extending between a first source/drain region and a second source/drain region, the semiconductor nanostructures comprising:
a first semiconductor nanostructure at a first distance from the substrate;
a second semiconductor nanostructure at a second distance from the substrate, wherein the second distance is greater than the first distance; and
a third semiconductor nanostructure at a third distance from the substrate, wherein the third distance is greater than the second distance, wherein thicknesses of the semiconductor nanostructures gradually increase as distances between the substrate and the semiconductor nanostructures increase;
gate dielectric layers encircling the semiconductor nanostructures; and
a gate electrode encircling the semiconductor nanostructures, wherein the gate dielectric layers separate the gate electrode from the semiconductor nanostructures, wherein a first portion of the gate electrode and a second portion of the gate electrode are separated by the third semiconductor nanostructure, wherein a first spacer extends along a first sidewall of the first portion of the gate electrode, wherein a second spacer extends along a first sidewall of the second portion of the gate electrode, and wherein the first spacer and the second spacer comprise different materials.
13. The semiconductor device of claim 12 , wherein a bottom surface of the first source/drain region is below an interface between the gate dielectric layers and the substrate.
14. The semiconductor device of claim 12 , wherein a first gate dielectric layer of the gate dielectric layers extends between the first spacer and the first portion of the gate electrode, and wherein a second gate dielectric layer of the gate dielectric layers extends between the second spacer and the second portion of the gate electrode.
15. The semiconductor device of claim 12 , wherein the first semiconductor nanostructure has a first thickness, wherein the third semiconductor nanostructure has a third thickness, and wherein a difference between the first thickness and the third thickness is in a range from 1 nm to 6 nm.
16. The semiconductor device of claim 12 , wherein the first semiconductor nanostructure has a first thickness, wherein the third semiconductor nanostructure has a third thickness, and wherein a ratio of the third thickness to the first thickness is in a range from 1.1 to 1.69.
17. The semiconductor device of claim 12 , wherein the first semiconductor nanostructure is spaced apart from the second semiconductor nanostructure by a fourth distance, wherein the second semiconductor nanostructure is spaced apart from the third semiconductor nanostructure by a fifth distance, and wherein the fourth distance and the fifth distance equal to the first distance.
18. The semiconductor device of claim 12 , further comprising a gate via disposed over the semiconductor nanostructures, wherein the third semiconductor nanostructure is a semiconductor nanostructure closest to the gate via.
19. The device of claim 1 , wherein the bottom nanostructure has a third thickness, wherein the top nanostructure has a first thickness, and wherein a ratio of the first thickness to the third thickness is in a range from 1.1 to 1.69.
20. The device of claim 1 , wherein a first portion of the gate dielectric extends between the first spacer and the first sidewall of the first portion of the gate electrode, and wherein a second portion of the gate dielectric extends between the second spacer and the first sidewall of the second portion of the gate electrode.