IP Library Granted Patent US 12,372,864
Granted Patent B2
US 12,372,864 · App. 16/949,270 · Granted Jul 29, 2025

Methods and systems to determine shapes for semiconductor or flat panel display fabrication

Inventors: Akira Fujimura (Saratoga, CA); Nagesh Shirali (San Jose, CA); Donald Oriordan (Sunnyvale, CA)
Assignee: D2S, INC.
G06F30/398G03F1/36G03F7/70441G06N3/04G06N3/08
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,372,864
App. No.
16/949,270
Granted
Jul 29, 2025
Kind
B2
Abstract

Methods for calculating a pattern to be manufactured on a substrate include inputting a physical design pattern, determining a plurality of possible neighborhoods for the physical design pattern, generating a plurality of possible mask designs for the physical design pattern, calculating a plurality of possible patterns on the substrate, calculating a variation band from the plurality of possible patterns, and modifying the physical design pattern to reduce the variation band. Embodiments also include inputting a set of parameters for a neural network to calculate a pattern to be manufactured on a substrate, calculating a plurality of patterns to be manufactured on the substrate for the physical design in each possible neighborhood of the plurality of possible neighborhoods, training the neural network with the calculated plurality of patterns, and adjusting the set of parameters to reduce the manufacturing variation for the calculated plurality of patterns to be manufactured on a substrate.

Claims (47)

1. A method for calculating a pattern to be manufactured on a substrate used to create an integrated circuit (IC), the method comprising:

receiving a physical design pattern produced by a computer aided design application to represent a portion of a circuit design of the IC;

determining a plurality of possible neighborhoods for the physical design pattern;

generating a plurality of possible mask designs for the physical design pattern, wherein the plurality of possible mask designs corresponds to the plurality of possible neighborhoods;

calculating a plurality of possible patterns on the substrate, wherein the plurality of possible patterns on the substrate correspond to the plurality of possible mask designs;

calculating a variation band from the plurality of possible patterns on the substrate; and

modifying the physical design pattern to reduce the variation band.

2. The method of claim 1 further comprising calculating a plurality of mask images from the plurality of possible mask designs.

3. The method of claim 2 , wherein calculating the plurality of possible mask images comprises performing charged particle beam simulation.

4. The method of claim 1 , wherein modifying the physical design pattern comprises modifying the plurality of possible neighborhoods of the physical design pattern.

5. The method of claim 1 , wherein the variation band corresponds to a set of manufacturing variation parameters.

6. The method of claim 1 , wherein the variation band comprises a process variation with a lower bound and an upper bound surrounding a nominal substrate pattern.

7. The method of claim 1 further comprising performing a coloring step separating shapes of the physical design pattern into layers.

8. The method of claim 7 , wherein modifying the physical design pattern includes modifying the coloring step.

9. The method of claim 1 , wherein generating the plurality of possible mask designs comprises performing optical proximity correction (OPC) of the physical design pattern.

10. The method of claim 1 , wherein determining the plurality of possible neighborhoods, generating the plurality of possible mask designs, or calculating the plurality of possible patterns on the substrate comprises using a neural network.

11. The method of claim 10 further comprising using post- processing to aggregate variation in the variation band.

12. The method of claim 10 , wherein the neural network further comprises multiple output channels to aggregate variation in the variation band.

13. The method of claim 1 further comprising calculating false negatives and false positives for the plurality of possible patterns on the substrate.

14. The method of claim 1 , wherein calculating the plurality of possible patterns on the substrate comprises performing lithography simulation.

15. The method of claim 1 , wherein the physical design pattern comprises a portion of an entire design, wherein the method further comprises determining a set of actual neighborhoods in which the physical design pattern is used in the entire design.

16. The method of claim 15 , wherein the portion of the entire design is an instance of the physical design pattern and the plurality of possible neighborhoods includes all neighborhoods of each instance.

17. The method of claim 1 , wherein each possible neighborhood in the plurality of possible neighborhoods is one possible neighborhood that surrounds the physical design pattern, wherein the plurality of possible neighborhoods comprise different shapes or different orientations of shapes.

18. A non-transitory machine readable medium storing a program for calculating a pattern to be manufactured on a substrate used to create an integrated circuit (IC), the program for execution by at least one processing unit, the program comprising sets of instructions for:

receiving a physical design pattern produced by a computer aided design application to represent a portion of a circuit design of the IC;

determining a plurality of possible neighborhoods for the physical design pattern;

generating, for the received physical design pattern, a plurality of possible mask designs corresponding to the plurality of possible neighborhoods;

calculating a plurality of possible patterns that are expected to be produced on the substrate for the plurality of possible mask designs;

calculating a variation band that expresses a difference between the plurality of possible patterns that are expected to be produced on the substrate; and

directing a physical design tool to modify the physical design pattern in order to reduce the variation band.

19. The non-transitory machine readable medium of claim 18 , wherein the program further comprises a set of instructions for calculating a plurality of mask images from the plurality of possible mask designs.

20. The non-transitory machine readable medium of claim 18 , wherein the physical design tool modifies the physical design pattern by modifying the plurality of possible neighborhoods of the physical design pattern.

21. The non-transitory machine readable medium of claim 18 , wherein the variation band comprises a process variation with a lower bound and an upper bound surrounding a nominal substrate pattern.

22. The non-transitory machine readable medium of claim 18 , wherein the set of instructions for at least one of determining the plurality of possible neighborhoods, generating the plurality of possible mask designs, or calculating the plurality of possible patterns that are expected to be produced on the substrate comprises a set of instructions for using a neural network.

23. A method for modifying a physical design pattern to be manufactured on a substrate, the physical design pattern part of an integrated circuit (IC) design layout and produced by a computer design application to represent a portion of a circuit design of the IC, the method comprising:

calculating, for the physical design pattern produced by the computer design application to represent the portion of the circuit design of the IC, a plurality of possible patterns that are predicted to be manufactured on the substrate based on different possible neighborhoods for the physical design pattern in the IC design layout;

calculating a variation band from the plurality of possible patterns on the substrate; and

modifying the physical design pattern in order to reduce the variation band.

24. The method of claim 23 , wherein the plurality of possible patterns is further based on variations in at least one manufacturing process parameter.

25. The method of claim 23 further comprising generating a plurality of possible mask designs for the physical design pattern, wherein the plurality of possible mask designs corresponds to the plurality of possible neighborhoods.

26. A method for calculating a pattern to be manufactured on a substrate, the method comprising:

receiving a physical design pattern;

determining a plurality of possible neighborhoods for the physical design pattern;

generating a plurality of possible mask designs for the physical design pattern, wherein the plurality of possible mask designs corresponds to the plurality of possible neighborhoods;

using a neural network to calculate a plurality of possible patterns on the substrate, wherein the plurality of possible patterns on the substrate correspond to the plurality of possible mask designs, and the neural network comprises a plurality of output channels each of which outputs a different calculated possible pattern;

calculating a variation band from the plurality of possible patterns on the substrate; and

modifying the physical design pattern to reduce the variation band.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2021
From: FUJIMURA, AKIRA; SHIRALI, NAGESH; ORIORDAN, DONALD
To: D2S, INC.
Reel/Frame 055250/0471 →
Continuity (1)
Related Publication 20220128899A1 · Apr 28, 2022
References Cited (156)
US 5698346A · Sugawara · 1997 [cited by applicant]
US 6042257A · Tsudaka · 2000 [cited by applicant]
US 7269817B2 · Heng · 2007 [cited by examiner]
US 7353493B2 · Akiyama · 2008 [cited by applicant]
US 7355673B2 · Hsu et al. · 2008 [cited by applicant]
US 7401319B2 · Horng · 2008 [cited by examiner]
US 7526748B2 · Kotani et al. · 2009 [cited by applicant]
US 7754401B2 · Fujimura et al. · 2010 [cited by applicant]
US 7921383B1 · Wei · 2011 [cited by examiner]
US 8166423B2 · Mansfield · 2012 [cited by examiner]
US 8336006B2 · Kodera · 2012 [cited by examiner]
US 8429573B2 · Ogino et al. · 2013 [cited by applicant]
US 8473875B2 · Fujimura et al. · 2013 [cited by applicant]
US 8667443B2 · Smayling · 2014 [cited by examiner]
US 8719739B2 · Fujimura · 2014 [cited by examiner]
US 8818072B2 · Ong · 2014 [cited by examiner]
US 9355204B2 · Seo · 2016 [cited by examiner]
US 9430442B2 · Iyer · 2016 [cited by examiner]
US 9922161B2 · Kahng et al. · 2018 [cited by applicant]
US 10012900B2 · Kim · 2018 [cited by examiner]
US 10346740B2 · Zhang et al. · 2019 [cited by applicant]
US 10444629B2 · Zable · 2019 [cited by applicant]
US 10520830B2 · Kicken · 2019 [cited by examiner]
US 10670973B2 · Zou · 2020 [cited by examiner]
US 10678142B2 · Jheng · 2020 [cited by examiner]
US 10762267B2 · Kamon · 2020 [cited by examiner]
US 10923318B2 · Gledhill · 2021 [cited by examiner]
US 11043359B2 · Nakamura · 2021 [cited by examiner]
US 20040210863A1 · Culp et al. · 2004 [cited by applicant]
US 20050132306A1 · Smith et al. · 2005 [cited by applicant]
US 20050251771A1 · Robles · 2005 [cited by applicant]
US 20060190911A1 · Stivers · 2006 [cited by examiner]
US 20070235665A1 · Shamoun · 2007 [cited by examiner]
US 20080109766A1 · Song et al. · 2008 [cited by applicant]
US 20110061030A1 · Mansfield et al. · 2011 [cited by applicant]
US 20110089345A1 · Komagata et al. · 2011 [cited by applicant]
US 20120051621A1 · Ong · 2012 [cited by examiner]
US 20120151422A1 · White et al. · 2012 [cited by applicant]
US 20130022929A1 · Komagata et al. · 2013 [cited by applicant]
US 20130070222A1 · Fujimura · 2013 [cited by applicant]
US 20130159943A1 · Agarwal et al. · 2013 [cited by applicant]
US 20130283216A1 · Pearman et al. · 2013 [cited by applicant]
US 20130283218A1 · Fujimura · 2013 [cited by examiner]
US 20160125120A1 · Yu et al. · 2016 [cited by applicant]
US 20170194126A1 · Bhaskar et al. · 2017 [cited by applicant]
US 20170357911A1 · Liu et al. · 2017 [cited by applicant]
US 20180067900A1 · Mos et al. · 2018 [cited by applicant]
US 20180374677A1 · Fay et al. · 2018 [cited by applicant]
US 20190146355A1 · Jheng · 2019 [cited by examiner]
US 20190197213A1 · Ungar · 2019 [cited by applicant]
US 20190206041A1 · Fang et al. · 2019 [cited by applicant]
US 20190377849A1 · Sha et al. · 2019 [cited by applicant]
US 20190385300A1 · Baidya et al. · 2019 [cited by applicant]
US 20200051781A1 · Fujimura · 2020 [cited by examiner]
US 20200065453A1 · Kim et al. · 2020 [cited by applicant]
US 20200134131A1 · Tien et al. · 2020 [cited by applicant]
US 20200184137A1 · Tsutsui et al. · 2020 [cited by applicant]
US 20200279065A1 · Ungar · 2020 [cited by examiner]
US 20200326632A1 · Fang et al. · 2020 [cited by applicant]
US 20200380089A1 · Gheith et al. · 2020 [cited by applicant]
US 20200380362A1 · Cao et al. · 2020 [cited by applicant]
US 20200387660A1 · Cecil · 2020 [cited by applicant]
US 20210141988A1 · Ungar · 2021 [cited by examiner]
US 20210181620A1 · Poonawala et al. · 2021 [cited by applicant]
US 20210216697A1 · Brink et al. · 2021 [cited by applicant]
US 20210232748A1 · Hsu · 2021 [cited by examiner]
US 20210048741A1 · Lugg et al. · 2021 [cited by applicant]
US 20210279878A1 · Adler et al. · 2021 [cited by applicant]
US 20210364450A1 · Lauber · 2021 [cited by examiner]
US 20210397172A1 · Slachter et al. · 2021 [cited by applicant]
US 20220035237A1 · Lee · 2022 [cited by examiner]
US 20220050381A1 · Biswas et al. · 2022 [cited by applicant]
US 20220187713A1 · Middlebrooks · 2022 [cited by examiner]
US 20220299881A1 · Zheng et al. · 2022 [cited by applicant]
US 20230024684A1 · Fujimura et al. · 2023 [cited by applicant]
US 20230027655A1 · Fujimura et al. · 2023 [cited by applicant]
US 20230032510A1 · Fujimura et al. · 2023 [cited by applicant]
US 20230107556A1 · Tao · 2023 [cited by examiner]
US 20230186009A1 · Fujimura et al. · 2023 [cited by applicant]
CN 104051234A · 2014 [cited by examiner]
CN 107065447A · 2017 [cited by examiner]
CN 107438842A · 2017 [cited by examiner]
CN 111758072A · 2020 [cited by examiner]
CN 113168085A · 2021 [cited by examiner]
CN 113168115A · 2021 [cited by examiner]
EP 3951496A1 · 2022 [cited by examiner]
EP 4205176A1 · 2023 [cited by applicant]
JP H08202020A · 1996 [cited by applicant]
JP H08248614A · 1996 [cited by applicant]
JP 2001174974A · 2001 [cited by applicant]
JP 2004341160A · 2004 [cited by applicant]
JP 2006053248A · 2006 [cited by applicant]
JP 2007536581A · 2007 [cited by examiner]
JP 2009170743A · 2009 [cited by applicant]
JP 2010146024A · 2010 [cited by applicant]
JP 2012181298A · 2012 [cited by applicant]
JP 2014530494A · 2014 [cited by applicant]
JP 2021509208A · 2021 [cited by examiner]
KR 1020190004000A · 2019 [cited by applicant]
KR 102170578B1 · 2020 [cited by examiner]
KR 20210010897A · 2021 [cited by examiner]
KR 102377411B1 · 2022 [cited by examiner]
TW 201346436A · 2013 [cited by examiner]
TW 201423287A · 2014 [cited by examiner]
TW 201905578A · 2019 [cited by applicant]
TW 1710763B · 2020 [cited by examiner]
TW 202113501A · 2021 [cited by applicant]
TW 202121050A · 2021 [cited by applicant]
WO WO2019115426A1 · 2019 [cited by examiner]
WO 2020193095A1 · 2020 [cited by applicant]
WO WO2021043936A1 · 2021 [cited by examiner]
WO 2022086825A1 · 2022 [cited by applicant]
Ibtehaz and Rahman, MultiRestUNet: Rethinking the U-Net Architecture for Multimodal Biomedical Image Segmentation, Feb. 2019, https://arxiv.org/pdf/1902.04049.pdf. [cited by applicant]
Ronneberger et al., U-Net: Convolutional Networks for Biomedical Image Segmentation, May 2015, https://arxiv.org/pdf/1505.04597.pdf. [cited by applicant]
Ao, Jianchang, et al., “Delay-Driven Layer Assignment in Global Routing under Multi-tier Interconnect Structure,” Mar. 2013, 7 pages, ACM, retrieved from https://dl.acm.org/doi/10.1145/2451916.2451942. [cited by applicant]
Author Unknown, “Deep reinforcement learning,” Wikipedia, Jun. 16, 2022, 6 page, Wikipedia.com. [cited by applicant]
Author Unknown, “Jaccard index,” Wikipedia, Jun. 19, 2022, 9 page, Wikipedia.com. [cited by applicant]
Chen, Tai-Chen, “Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction,” Jun. 2007, 13 pages, IEEE, retrieved from http://cc.ee.ntu.edu.tw/˜ywchang/Papers/tcad07-mgr.pdf. [cited by applicant]
Dai, Wayne Wei-Ming, “Rubber band routing and dynamic data representation,” 1990 IEEE International Conference on Computer-Aided Design, Nov. 11-15, 1990, 2 pages, IEEE, Santa Clara, California, USA. [cited by applicant]
Elmore, W.C., “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers,” Journal of Applied Physics, Jan. 1948, 9 pages, retrieved from http://algos.inesc-id.pt/projectos/exachip/r… [cited by applicant]
Kwan, Joe, et al., “Applying Machine Learning Techniques to Accelerate Advanced Process Yield Ramp,” Jan. 5, 2021, 29 pages, Siemens Digital Industries Software, Munich, Germany. [cited by applicant]
Lin, Yibo, et al., “Machine Learning for Yield Learning and Optimization,” ECE Department, University of Texas, Jul. 15, 2021, 10 pages, IEEE, Austin, Texas, USA. [cited by applicant]
Mitchell, Robin, “Imec Demonstrates Buried Power Rails in FinFET CMOS,” Mar. 17, 2021, 6 pages, EPM, retrieved from https://www.electropages.com/blog/2021/03/imec-demonstrates-buried-power-rails-finfet-cmos. [cited by applicant]
Mitra, Joydeep, “Radar: RET-Aware Detailed Routing Using Fast Lithography Simulations,” Proceedings 2005, 42nd Design Automation Conference, Jun. 13-17, 2005, 6 pages, IEEE, retrieved from https://citeseerx.ist.psu.edu/… [cited by applicant]
Pang, Linyong, et al., “How GPU-Accelerated Simulation Enables Applied Deep Learning for Masks and Wafers,” Month Unknown 2019, 10 pages, D2S, Inc., San Jose, California, USA. [cited by applicant]
Pang, Linyong, et al., “Making Digital Twins using the Deep Learning Kit (DLK),” Month Unknown 2019, 13 pages, D2S, Inc., San Jose, California, USA. [cited by applicant]
PCT International Search Report and Written Opinion of Commonly Owned International Patent Application PCT/US2021/055319 (D2S.P0001PCT), mailing date Feb. 17, 2022, 17 pages, International Searching Authority (US). [cited by applicant]
Pearman, Ryan, et al., “Adopting curvilinear shapes for production ILT: challenges and opportunities,” Month Unknown, 14 pages, D2S, Inc., retrieved from https://design2silicon.com/wp-content/uploads/2019/11/Manuscript_… [cited by applicant]
Li, Yongfu et al., “Advanced In-Design Auto-Fixing Flow for Cell Abutment Pattern Matching Weakpoints” Synopsys Jsers Group 2017, May 2018, 11 pages, retrieved from https://www.researchgate.net/publication/325414052_Adv… [cited by applicant]
Prasad, Divya, “Can we Bury our Scaling Problems with Buried Power Rails and Back-side Power Delivery?,” Mar. 5, 2020, 8 pages, Arm Limited, retrieved from https://community.arm.com/arm-research/b/articles/posts/can-we-… [cited by applicant]
Ren, Haoxing (Mark), “Machine Learning and Deep Learning Applications in Design Automation and Practical Issues,” Dac 19 Tutorial, Month Unknown 2019, 55 pages, Nvidia Corporation, Santa Clara, California, USA. [cited by applicant]
Teig, S., “The X architecture: not your father's diagonal wiring, ” SLIP '02: Proceedings of the 2002 international workshop on System-level interconnect prediction, Apr. 6, 2002, 4 pages, ACM, retrieved from https://dl… [cited by applicant]
Jia, Ningning, et al., “Machine Learning for Inverse Lithography: using stochastic gradient descent for robust photomask synthesis,” Journal of Optics, Apr. 1, 2010, 9 pages, vol. 12, IOP Publishing, retrieved from http… [cited by applicant]
Pang, Linyong, “Inverse Lithography Technology: 30 years from concept to practical, full-chip reality,” Journal of Micro/Nanopatterning, Materials, and Metrology, Aug. 31, 2021, 49 pages, vol. 20(3), SPIE, retrieved fro… [cited by applicant]
Cecil, Thomas, et al., “Establishing Fast, Practical, Full-Chip ILT Flows Using Machine Learning,” SPIE Proceedings 11327, Optical Microlithography XXXIII, Mar. 23, 2020, 19 pages, vol. 1132706, SPIE, San Jose, Californ… [cited by applicant]
Chen, Kun-Yuan, et al., “Full-Chip Application of Machine Learning SRAFs on DRAM Case Using Auto Pattern Selection,” SPIE Proceedings 10961, Optical Microlithography XXXII, Oct. 10, 2019, 13 pages, vol. 1096108, SPIE, S… [cited by applicant]
Feng, Yaobin, et al., “Freeform Mask Optimization Using Advanced Image based M3D Inverse Lithography and 3D- Nand Full Chip OPC Application,” SPIE Proceedings 10587, Optical Microlithography XXXI, Mar. 20, 2018, 11 page… [cited by applicant]
Liu, Peng, “Mask Synthesis Using Machine Learning Software and Hardware Platforms,” SPIE Proceedings 11327, Optical Microlithography XXXIII, Mar. 23, 2020, 17 pages, vol. 1132707, SPIE, San Jose, California, USA. [cited by applicant]
Shi, Xuelong, et al., “Physics based feature Vector Design: a Critical Step Towards Machine Learning based Inverse Lithography,” SPIE Proceedings 11327, Optical Microlithography XXXIII, Mar. 23, 2020, 8 pages, vol. 1132… [cited by applicant]
Wang, Shibing, et al., “Efficient Full-Chip SRAF Placement Using Machine Learning for Best Accuracy and Improved Consistency,” SPIE Proceedings 10587, Optical Microlithography XXXI, Mar. 20, 2018, 10 pages, vol. 105870N… [cited by applicant]
Wang, Shibing, et al., “Machine Learning Assisted SRAF Placement for Full Chip,” SPIE Proceedings 10451, Photomask Technology 2017, Oct. 16, 2017, 8 pages, vol. 104510D, SPIE, Monterey, California, USA. [cited by applicant]
Ajayi, Tutu, et al., “OpenROAD: Toward a Self-Driving, Open-Source Digital Layout Implementation Tool Chain,” Proceedings of Government Microcircuit Applications and Critical Technology Conference, Jan. 1, 2019, 6 pages… [cited by applicant]
Author Unknown, “D2S Enables ”Stitchless“ Full-Chip Inverse Lithography Technology in a Single Day for the Multi-Beam Era,” Press Release, Sep. 16, 2019, 3 pages, D2S, Inc., San Jose, California, USA. [cited by applicant]
Author Unknown, “D2S Unveils Industry's First Mask-Wafer Double Simulation Platform,” Press Release, Sep. 20, 2011, 3 pages, D2S, Inc., San Jose, California, USA. [cited by applicant]
Author Unknown, “Multiple patterning,” Wikipedia, Oct. 10, 2020, 22 pages, Wikipedia.com. [cited by applicant]
Author Unknown, “Optical proximity correction,” Wikipedia, Apr. 28, 2019, 5 pages, Wikipedia.com. [cited by applicant]
Author Unknown, “Rasterisation,” Wikipedia, Aug. 21, 2020, 4 pages, Wikipedia.com. [cited by applicant]
Author Unknown, “TrueMask® DS,” Exact Date Unknown but Before May 2020, 3 pages, D2S, Inc., retrieved from https://design2silicon.com/products/truemask-ds/. [cited by applicant]
Author Unknown, “TrueMask® ILT Backgrounder Stitchless Full-Chip ILT in a Day,” Backgrounder, Sep. 2019, 6 pages, D2S, Inc., San Jose, California, USA. [cited by applicant]
Author Unknown, “TrueMask® ILT,” Exact Date Unknown but Before May 2020, 7 pages, D2S, Inc., retrieved from https://design2silicon.com/products/truemask-ilt/. [cited by applicant]
Pang, Linyong (Leo), et al., “Study of Mask and Wafer Co-design That Utilizes a New Extreme SIMD Approach to Computing in Memory Manufacturing: Full-Chip Curvilinear ILT in a Day,” SPIE Proceedings 11148, Photomask Tech… [cited by applicant]
Pradipta, Geraldo, et al., “A Machine Learning Based Parasitic Extraction Tool,” Oct. 31, 2019, 3 pages, University of Minnesota, Minneapolis, Minnesota, USA. [cited by applicant]
Sole, Marc Pons, “Layout Regularity for Design and Manufacturability,” Doctoral Thesis, Jul. 8, 2012, 185 pages, Technical University of Catalonia, Barcelona, Spain. [cited by applicant]
Sperling, Ed, “Design Rule Complexity Rising,” Semiconductor Engineering - Deep Insights for the Tech Industry, Apr. 19, 2018, 16 pages, SMG, retrieved from https://semiengineering.com/design-rule-complexity-rising/. [cited by applicant]
Yang, Dingcheng, et al., “CNN-Cap: Effective Convolutional Neural Network Based Capacitance Models for Full- Chip Parasitic Extraction,” Jul. 14, 2021, 9 pages, retrieved from https://arxiv.org/pdf/2107.06511.pdf. [cited by applicant]
Tripathi, Vikas, et al., “Context-Aware DFM Rule Analysis and Scoring Using Machine Learning,” Aug. 16, 2018, 9 pages, retrieved from https://arxiv.org/pdf/1808.05999.pdf. [cited by applicant]
Cited By (1)
US 12,547,808