Computing parasitic values for semiconductor designs
Some embodiments provide a method for calculating parasitic parameters for a pattern to be manufactured on an integrated circuit (IC) substrate. The method receives a definition of a wire structure as input. The method rasterizes the wire structure (e.g., produces pixel-based definition of the wire structure) to produce several images. Before rasterizing the wire structure, the method in some embodiments decomposes the wire structure into several components (e.g., several wires, wire segments or wire structure portions), which it then individually rasterizes. The method then uses the images as inputs to a neural network, which then calculates parasitic parameters associated with the wire structure. In some embodiments, the parasitic parameters include unwanted parasitic capacitance effects exerted on the wire structure. Conjunctively, or alternatively, these parameters include unwanted parasitic resistance and/or inductance effects on the wire structure.
1. A method for calculating parasitic parameters for wire structures that are to be manufactured on a semiconductor substrate and that are to be defined in one or more semiconductor designs, the method comprising:
receiving a first wire structure that includes a plurality of rectilinear shapes associated with one or more semiconductor designs;
generating, from the first wire structure, a second wire structure comprising a plurality of curvilinear shapes; and
using the second wire structure to generate parasitic parameters for specifying parasitic effects experienced by one or more wire structures of the one or more semiconductor designs.
2. The method of claim 1 , wherein the second wire structure with the curvilinear shapes is a structure that is predicted to be produced once the first wire structure is manufactured, and is thereby a predicted manufactured structure of the first wire structure.
3. The method of claim 2 , wherein generating the second wire structure comprises supplying the first wire structure to a machine-trained network to produce the second wire structure.
4. The method of claim 3 , wherein the machine-trained network is a neural network with a plurality of machine-trained neurons.
5. The method of claim 2 , wherein generating the second wire structure comprises using a software simulator to generate the second wire structure as the predicted manufactured structure.
6. The method of claim 1 , wherein the first and second wire structures are defined to include two-dimensional (2D) shapes, the method further comprising:
receiving a set of manufacturing process technology information associated with the semiconductor design;
using the set of manufacturing process technology information to produce a three-dimensional (3-D) shape from the second wire structure; and
providing the 3-D shape to a field solver to produce a set of parasitic parameters.
7. The method of claim 6 , wherein the set of manufacturing process technology information comprises wire heights and dielectric thickness.
8. The method of claim 6 , wherein the set of parasitic parameters are used to train a machine-trained network to produce parasitic coefficients for different wire structures of different semiconductor designs, the method further comprising:
extracting a particular wire structure from a particular semiconductor design;
rasterizing the particular wire structure to produce a pixel-based definition of the particular wire structure;
supplying the pixel-based definition to the machine-trained network to produce a plurality of parasitic coefficients for the particular wire structure; and
using the produced plurality of parasitic coefficients to compute a parasitic value that represents a parasitic effect on the particular wire structure.
9. The method of claim 6 , wherein the set of parasitic parameters are used to train a machine-trained network to produce parasitic values for different wire structures of different semiconductor designs, the method further comprising
extracting a particular wire structure from a particular semiconductor design;
dividing the particular wire structure with a tile structure that comprises a plurality of tiles, the divided particular wire structure comprising a plurality of wire structures each of which falls within a different tile;
rasterizing each of the plurality of wire structures to produce a pixel-based definition of each wire structure;
supplying each pixel-based definition to the machine-trained network to produce a tile-specific parasitic value; and
computing an overall parasitic value from the produced tile-specific parasitic values, the overall parasitic value representing a parasitic effect on the particular wire structure.
10. The method of claim 1 , wherein rectilinear shapes comprise shapes that are produced by using straight line segments, while curvilinear shapes are shapes that are produced by using at least one curved line segment.
11. A non-transitory machine-readable medium storing a program which when executed by at least one processing unit calculates parasitic parameters for wire structures that are to be manufactured on a semiconductor substrate and that are to be defined in one or more semiconductor designs, the program comprising sets of instructions for:
receiving a first wire structure that includes a plurality of rectilinear shapes associated with one or more semiconductor designs;
generating, from the first wire structure, a second wire structure comprising a plurality of curvilinear shapes; and
using the second wire structure to generate parasitic parameters for specifying parasitic effects experienced by one or more wire structures of the one or more semiconductor designs.
12. The non-transitory machine-readable medium of claim 11 , wherein the second wire structure with the curvilinear shapes is a structure that is predicted to be produced once the first wire structure is manufactured, and is thereby a predicted manufactured structure of the first wire structure.
13. The non-transitory machine-readable medium of claim 12 , wherein the set of instructions for generating the second wire structure comprises a set of instructions for supplying the first wire structure to a machine-trained network to produce the second wire structure.
14. The non-transitory machine-readable medium of claim 13 , wherein the machine-trained network is a neural network with a plurality of machine-trained neurons.
15. The non-transitory machine-readable medium of claim 12 , wherein the set of instructions for generating the second wire structure comprises a set of instructions for using a software simulator to generate the second wire structure as the predicted manufactured structure.
16. The non-transitory machine-readable medium of claim 11 , wherein the first and second wire structures are defined to include two-dimensional (2D) shapes, the program further comprising sets of instructions for:
receiving a set of manufacturing process technology information associated with the semiconductor design;
using the set of manufacturing process technology information to produce a three-dimensional (3-D) shape from the second wire structure; and
providing the 3-D shape to a field solver to produce a set of parasitic parameters.
17. The non-transitory machine-readable medium of claim 16 , wherein the set of manufacturing process technology information comprises wire heights and dielectric thickness.
18. The non-transitory machine-readable medium of claim 16 , wherein the set of parasitic parameters are used to train a machine-trained network to produce parasitic coefficients for different wire structures of different semiconductor designs, the program further comprising sets of instructions for:
extracting a particular wire structure from a particular semiconductor design;
rasterizing the particular wire structure to produce a pixel-based definition of the particular wire structure;
supplying the pixel-based definition to the machine-trained network to produce a plurality of parasitic coefficients for the particular wire structure; and
using the produced plurality of parasitic coefficients to compute a parasitic value that represents a parasitic effect on the particular wire structure.
19. The non-transitory machine-readable medium of claim 16 , wherein the set of parasitic parameters are used to train a machine-trained network to produce parasitic coefficients for different wire structures of different semiconductor designs, the program further comprising sets of instructions for:
extracting a particular wire structure from a particular semiconductor design;
dividing the particular wire structure with a tile structure that comprises a plurality of tiles, the divided particular wire structure comprising a plurality of wire structures each of which falls within a different tile;
rasterizing each of the plurality of wire structures to produce a pixel-based definition of each wire structure;
supplying each pixel-based definition to the machine-trained network to produce a tile-specific parasitic value; and
computing an overall parasitic value from the produced parasitic values, the overall parasitic value representing a parasitic effect on the particular wire structure.
20. The non-transitory machine-readable medium of claim 11 , wherein rectilinear shapes comprise shapes that are produced by using straight line segments, while curvilinear shapes are shapes that are produced by using at least one curved line segment.