Leveraging concurrency to improve interactivity with an EDA tool
A method for manufacturing-aware editing of circuit layouts driven by predictions regarding predicted manufactured wafer contours generated by a machine-trained network. The method allows for fast edit loops in interactive editing timeframes, in which the predicted manufactured wafer contours corresponding to design edits are presented within seconds of the edits themselves. In some embodiments, the wafer contours take mask OPC/ILT and lithography effects into account, as determined by the machine trained network.
1 . A method for defining an integrated circuit (IC) design layout comprising a plurality of components, each component having a shape in the design layout, the method comprising:
concurrently:
using a first independent execution sequence to edit the IC design layout;
using a second independent execution sequence to divide and rasterize the design layout produced by the first independent execution sequence into a plurality of tiles that are defined in a pixel domain instead of a contour geometric domain used by the first independent execution sequence; and
using a third independent execution sequence to receive a particular tile, to produce for each particular component in the particular tile an expected manufactured shape of the particular component from the particular component's shape in the design layout, and to provide the expected manufactured shapes of the components in the particular tile back to the first independent execution sequence to use in editing the IC design layout.
2 . The method of claim 1 , wherein the first independent execution sequence generates a display of the expected manufactured shapes for presentation on a display screen.
3 . The method of claim 1 , wherein the first independent execution sequence uses the expected manufactured shapes for a design operation performed by the first independent execution sequence.
4 . The method of claim 3 , wherein the design operation that uses the expected manufactured shapes is a design rule check (DRC) operation.
5 . The method of claim 1 , wherein using the first independent execution sequence comprises using the first independent execution sequence to bias the design.
6 . A method for defining an integrated circuit (IC) design layout comprising a plurality of components, each component having a shape in the design layout, the method comprising:
concurrently:
using a first independent execution sequence to edit the IC design layout;
using a second independent execution sequence to divide the IC design layout into tiles; and
using a third independent execution sequence to receive a particular tile, to produce for each particular component in the particular tile an expected manufactured shape of the particular component from the particular component's shape in the design layout, and to provide the expected manufactured shapes of the components in the particular tile back to the first independent execution sequence to use in editing the IC design layout, wherein using the third independent execution sequence comprises using the third independent execution sequence to execute a machine-trained network that is trained through a training process to produce, from a pixel-definition of the particular tile of the IC design layout, a pixel-definition of the manufactured shapes of the components within the particular tile.
7 . The method of claim 6 , wherein using the third independent execution sequence comprises performing a stitching operation to reconstruct the IC design layout from tile outputs that the machine-trained network produces for the tiles.
8 . The method of claim 7 , wherein using the second independent execution sequence comprises using the second independent execution sequence to convert a pixel-definition of the IC design layout to a geometric contour definition in which each shape is defined by reference to one or more defined contours of the shape.
9 . The method of claim 1 , wherein using the third independent execution sequence comprises
using the third independent execution sequence to process a first tile in order to produce expected manufactured shapes of the IC design layout within the first tile; and
using a fourth independent execution sequence to process a second tile in order to produce expected manufactured shapes of the IC design layout within the second tile.
10 . The method of claim 1 , wherein each independent execution sequence is a separate process from the other execution sequences.
11 . The method of claim 1 , wherein each independent execution sequence is a separate process that has a separate memory allocation in a memory space of a computer from other processes that are other independent execution sequences.
12 . The method of claim 1 , wherein the first, second and third independent execution sequences are three separate threads of one process.
13 . A non-transitory machine readable medium storing a program that when executed by a set of one or more processing units of a computer define an integrated circuit (IC) design layout that comprises a plurality of components, each component having a shape in the design layout, the program comprising:
a first independent execution sequence to edit the IC design layout;
a second independent execution sequence to divide and rasterize the design layout produced by the first independent execution sequence into a plurality of tiles that are defined in a pixel domain instead of a contour geometric domain used by the first independent execution unit; and
a third independent execution sequence to receive a particular tile, to produce for each particular component in the particular tile an expected manufactured shape of the particular component from the particular component's shape in the design layout, and to provide the expected manufactured shapes of the components in the particular tile back to the first independent execution sequence,
wherein the first, second and third independent execution sequences executed concurrently on the computer,
wherein the first independent execution sequence uses the expected manufactured shapes of the components in the particular tile to perform a design operation.
14 . The non-transitory machine readable medium of claim 13 , wherein the first independent execution sequence further generates a display of the expected manufactured shapes for presentation on a display screen.
15 . The non-transitory machine readable medium of claim 13 , wherein the third independent execution sequence executes a machine-trained network that from a pixel-definition of the IC design layout produced by the second independent execution sequence generates a pixel-definition of the manufactured shapes.
16 . The non-transitory machine readable medium of claim 15 , wherein the third independent execution sequence performs a stitching operation to reconstruct the IC design layout from tile outputs that the machine-trained network produces for the tiles.
17 . The method of claim 15 , wherein the second independent execution sequence converts a pixel-definition of the IC design layout to a geometric contour definition in which each shape is defined by reference to one or more defined contours of the shape.