IP Library Granted Patent US 12,664,340
Granted Patent B2
US 12,664,340 · App. 17/992,906 · Granted Jun 23, 2026

Interactively presenting for minimum overlap shapes in an IC design

Inventors: Donald Oriordan (Sunnyvale, CA); Akira Fujimura (Saratoga, CA); George Janac (Saratoga, CA)
Assignee: D2S, INC.
G06F30/31G06F30/392G06F30/398G06N3/08
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Quick Facts
Patent No.
US 12,664,340
App. No.
17/992,906
Filed
Nov 22, 2022
Granted
Jun 23, 2026
Kind
B2
Examiner
TAT, BINH C
Art Unit
2851
USPC
716/112
Abstract

Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.

Claims (31)

1 . A method of designing an integrated circuit (IC) with a plurality of circuit elements, the method comprising:

for a layout of an IC design that has a plurality of interconnect layers and a multi-layer interface (i) connecting at least two IC-design circuit elements on a set of at least two interconnect layers, and (ii) comprising at least two components on the set of interconnect layers:

generating an animation that steps through a plurality of minimum overlap shapes for the multi-layer interface, wherein:

the minimum overlap shapes are shapes that are predicted to be produced after a manufacturing stage of a manufacturing process that is used to manufacture a semiconductor circuit from the design layout;

the animation comprises a plurality of sets of contours, each set of contours specifying a different set of shapes for the components of the interfaces on the different layers for a different variation of a manufacturing parameter of the manufacturing process; and

generating the animation comprises generating, for each manufacturing parameter variation, a predicted overlap shape for the interface by intersecting shapes of the interface components on the different layers as defined by the set of contours that specify the shapes of the interface components for the manufacturing parameter variation, said animation showing different predicted overlap shapes that are predicted to be produced for the different variations of the manufacturing process; and

displaying the animation on a display screen to aid in an assessment of the design layout.

2 . The method of claim 1 , wherein generating the animation further comprises:

identifying different alignments of the interface components on the different layers; and

generating, for each identified alignment, a predicted overlap shape for the interface by intersecting shapes of the interface components on the different layers when the components are aligned based on the identified alignment.

3 . The method of claim 2 , wherein identifying the different alignments comprises using a set of two or more alignment settings that are defined with respect to a vertical axis in order to identify two or more alignments of the interface components on the different layers.

4 . The method of claim 3 , wherein the alignment setting set specifies a range of one or more misalignments between the interconnect layers of the IC design, wherein the interconnect layers correspond to wiring layers of the IC.

5 . The method of claim 2 , wherein each interconnect layer is defined by reference to an x-axis and a y-axis and each interface component on each layer has a two-dimensional (2D) shape defined in the x- and y-axes of the layer of the interface component, wherein intersecting the shapes for each identified alignment comprises intersecting the 2D shapes of the interface components as the shapes are aligned based on the identified alignment.

6 . The method of claim 2 , wherein generating the predicted overlap shape for each identified alignment comprises generating, for each identified alignment, a plurality of predicted overlap shapes that represent a range of possible overlap shapes that are predicted to be produced based on the different variations of the manufacturing parameter of the manufacturing process.

7 . The method of claim 1 , wherein the different set of shapes for each parameter variation is generated by a machine-trained network.

8 . The method of claim 1 , wherein displaying the animation comprises overlaying the animation over a display of the IC design layout.

9 . A non-transitory machine readable medium storing an electronic design automation (EDA) program for designing an integrated circuit (IC) with a plurality of circuit elements, the program for execution by at least one processing unit of a computer, the program comprising sets of instructions for:

for a layout of an IC design that has a plurality of interconnect layers and a multi-layer interface (i) connecting at least two IC-design circuit elements on a set of at least two interconnect layers, and (ii) comprising at least two components on the set of interconnect layers:

generating an animation that steps through a plurality of minimum overlap shapes for the multi-layer interface, wherein:

the minimum overlap shapes are shapes that are predicted to be produced after a manufacturing stage of a manufacturing process that is used to manufacture a semiconductor circuit from the design layout;

the animation comprises a plurality of sets of contours, each set of contours specifying a different set of shapes for the components of the interfaces on the different layers for a different variation of a manufacturing parameter of the manufacturing process; and

the set of instructions for generating the animation comprises a set of instructions for generating, for each manufacturing parameter variation, a predicted overlap shape for the interface by intersecting shapes of the interface components on the different layers as defined by the set of contours that specify the shapes of the interface components for the manufacturing parameter variation, said animation showing different predicted overlap shapes that are predicted to be produced for the different variations of the manufacturing process; and

displaying the animation on a display screen to aid in an assessment of the design layout.

10 . The non-transitory machine readable medium of claim 9 , wherein the set of instructions for generating the animation further comprises sets of instructions for:

identifying different alignments of the interface components on the different layers; and

generating, for each identified alignment, a predicted overlap shape for the interface by intersecting shapes of the interface components on the different layers when the components are aligned based on the identified alignment.

11 . The non-transitory machine readable medium of claim 10 , wherein the set of instructions for identifying the different alignments comprises a set of instructions for using a set of two or more alignment settings that are defined with respect to a vertical axis in order to identify two or more alignments of the interface components on the different layers.

12 . The non-transitory machine readable medium of claim 10 , wherein each interconnect layer is defined by reference to an x-axis and a y-axis and each interface component on each layer has a two-dimensional (2D) shape defined in the x- and y-axes of the layer of the interface component, wherein intersecting the shapes for each identified alignment comprises intersecting the 2D shapes of the interface components as the shapes are aligned based on the identified alignment.

13 . The non-transitory machine readable medium of claim 10 , wherein the set of instructions for generating the predicted overlap shape for each identified alignment comprises a set of instructions for generating, for each identified alignment, a plurality of predicted overlap shapes that represent a range of possible overlap shapes that are predicted to be produced based on the different variations of the manufacturing parameter of the manufacturing process.

14 . The non-transitory machine readable medium of claim 9 , wherein the different set of shapes for each parameter variation is generated by a machine-trained network.

15 . The non-transitory machine readable medium of claim 9 , wherein the set of instructions for displaying the animation comprises a set of instructions for displaying each predicted minimum overlap shape for a duration of time.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2023
From: ORIORDAN, DONALD; FUJIMURA, AKIRA; JANAC, GEORGE
To: D2S, INC.
Reel/Frame 063974/0087 →
Continuity (2)
Provisional Application 63300675 · Jan 19, 2022
Related Publication 20230229844A1 · Jul 20, 2023
References Cited (185)
US 6510730B1 · Phan et al. · 2003 [cited by applicant]
US 6892365B2 · Culp et al. · 2005 [cited by applicant]
US 7269817B2 · Heng et al. · 2007 [cited by applicant]
US 7526748B2 · Kotani et al. · 2009 [cited by applicant]
US 7754401B2 · Fujimura et al. · 2010 [cited by applicant]
US 8381155B1 · Fick · 2013 [cited by examiner]
US 8450804B2 · Sekar · 2013 [cited by examiner]
US 8473875B2 · Fujimura et al. · 2013 [cited by applicant]
US 8818072B2 · Ong et al. · 2014 [cited by applicant]
US 10012900B2 · Kim et al. · 2018 [cited by applicant]
US 10346740B2 · Zhang et al. · 2019 [cited by applicant]
US 10444629B2 · Zable · 2019 [cited by applicant]
US 10520830B2 · Kicken et al. · 2019 [cited by applicant]
US 10651054B2 · Or-Bach · 2020 [cited by examiner]
US 10670973B2 · Zou et al. · 2020 [cited by applicant]
US 10678142B2 · Jheng et al. · 2020 [cited by applicant]
US 10923318B2 · Gledhill et al. · 2021 [cited by applicant]
US 10949595B2 · Tsutsui et al. · 2021 [cited by applicant]
US 11043359B2 · Nakamura et al. · 2021 [cited by applicant]
US 20040210863A1 · Culp et al. · 2004 [cited by applicant]
US 20050132306A1 · Smith et al. · 2005 [cited by applicant]
US 20050251771A1 · Robles · 2005 [cited by applicant]
US 20060190911A1 · Stivers · 2006 [cited by applicant]
US 20080109766A1 · Song et al. · 2008 [cited by applicant]
US 20080134131A1 · Asano et al. · 2008 [cited by applicant]
US 20090193369A1 · Chan et al. · 2009 [cited by applicant]
US 20100205575A1 · Arora et al. · 2010 [cited by applicant]
US 20110049635A1 · Carlson · 2011 [cited by applicant]
US 20110089345A1 · Komagata et al. · 2011 [cited by applicant]
US 20120151422A1 · White et al. · 2012 [cited by applicant]
US 20130022929A1 · Komagata et al. · 2013 [cited by applicant]
US 20130159943A1 · Agarwal et al. · 2013 [cited by applicant]
US 20130283216A1 · Pearman et al. · 2013 [cited by applicant]
US 20130283218A1 · Fujimura et al. · 2013 [cited by applicant]
US 20150302134A1 · Berkens · 2015 [cited by applicant]
US 20160042111A1 · Chang · 2016 [cited by applicant]
US 20160125120A1 · Yu et al. · 2016 [cited by applicant]
US 20160162621A1 · Hamouda · 2016 [cited by applicant]
US 20160239601A1 · Morisaki et al. · 2016 [cited by applicant]
US 20160253450A1 · Kandel et al. · 2016 [cited by applicant]
US 20160283631A1 · Lin et al. · 2016 [cited by applicant]
US 20170061044A1 · Ning et al. · 2017 [cited by applicant]
US 20170194126A1 · Bhaskar et al. · 2017 [cited by applicant]
US 20170357911A1 · Liu et al. · 2017 [cited by applicant]
US 20180067900A1 · Mos et al. · 2018 [cited by applicant]
US 20180315723A1 · Singh et al. · 2018 [cited by applicant]
US 20190072846A1 · Lin et al. · 2019 [cited by applicant]
US 20190086200A1 · Amit · 2019 [cited by applicant]
US 20190146355A1 · Jheng et al. · 2019 [cited by applicant]
US 20190188356A1 · Zhang et al. · 2019 [cited by applicant]
US 20190197213A1 · Ungar · 2019 [cited by applicant]
US 20190206041A1 · Fang et al. · 2019 [cited by applicant]
US 20190354006A1 · Hu et al. · 2019 [cited by applicant]
US 20190377849A1 · Sha et al. · 2019 [cited by applicant]
US 20190385300A1 · Baidya et al. · 2019 [cited by applicant]
US 20190392106A1 · Northrop et al. · 2019 [cited by applicant]
US 20200006102A1 · Lin et al. · 2020 [cited by applicant]
US 20200051781A1 · Fujimura et al. · 2020 [cited by applicant]
US 20200065453A1 · Kim et al. · 2020 [cited by applicant]
US 20200134131A1 · Tien et al. · 2020 [cited by applicant]
US 20200184137A1 · Tsutsui et al. · 2020 [cited by applicant]
US 20200364394A1 · Yu et al. · 2020 [cited by applicant]
US 20200380089A1 · Gheith et al. · 2020 [cited by applicant]
US 20200380362A1 · Cao et al. · 2020 [cited by applicant]
US 20200387660A1 · Cecil · 2020 [cited by applicant]
US 20210048741A1 · Lugg et al. · 2021 [cited by applicant]
US 20210072635A1 · Ma et al. · 2021 [cited by applicant]
US 20210173996A1 · Hanchinal et al. · 2021 [cited by applicant]
US 20210181620A1 · Poonawala et al. · 2021 [cited by applicant]
US 20210216697A1 · Brink et al. · 2021 [cited by applicant]
US 20210279878A1 · Adler et al. · 2021 [cited by applicant]
US 20210397172A1 · Slachter et al. · 2021 [cited by applicant]
US 20220035237A1 · Lee et al. · 2022 [cited by applicant]
US 20220050381A1 · Biswas et al. · 2022 [cited by applicant]
US 20220128899A1 · Fujimura et al. · 2022 [cited by applicant]
US 20220187713A1 · Middlebrooks et al. · 2022 [cited by applicant]
US 20220299881A1 · Zheng et al. · 2022 [cited by applicant]
US 20230024684A1 · Fujimura et al. · 2023 [cited by applicant]
US 20230027655A1 · Fujimura et al. · 2023 [cited by applicant]
US 20230032510A1 · Fujimura et al. · 2023 [cited by applicant]
US 20230092665A1 · Fujimura et al. · 2023 [cited by applicant]
US 20230107556A1 · Tao et al. · 2023 [cited by applicant]
US 20230168590A1 · Sin et al. · 2023 [cited by applicant]
US 20230168660A1 · Oriordan et al. · 2023 [cited by applicant]
US 20230169245A1 · Oriordan et al. · 2023 [cited by applicant]
US 20230169246A1 · Oriordan et al. · 2023 [cited by applicant]
US 20230169247A1 · Oriordan et al. · 2023 [cited by applicant]
US 20230186009A1 · Fujimura et al. · 2023 [cited by applicant]
US 20230205972A1 · Oriordan et al. · 2023 [cited by applicant]
US 20230229836A1 · Oriordan et al. · 2023 [cited by applicant]
US 20230229840A1 · Oriordan et al. · 2023 [cited by applicant]
US 20230267265A1 · Oriordan · 2023 [cited by applicant]
US 20230274065A1 · Fujimura · 2023 [cited by applicant]
US 20230274066A1 · Fujimura · 2023 [cited by applicant]
US 20230274067A1 · Fujimura · 2023 [cited by applicant]
US 20230274068A1 · Fujimura · 2023 [cited by applicant]
US 20230274069A1 · Fujimura · 2023 [cited by applicant]
US 20230274070A1 · Fujimura · 2023 [cited by applicant]
US 20230274071A1 · Fujimura · 2023 [cited by applicant]
US 20230280659A1 · Fu · 2023 [cited by applicant]
US 20230281374A1 · Fujimura · 2023 [cited by applicant]
US 20230282635A1 · Fujimura · 2023 [cited by applicant]
US 20230306177A1 · Fujimura · 2023 [cited by applicant]
US 20230351087A1 · Oriordan et al. · 2023 [cited by applicant]
US 20230351088A1 · Oriordan et al. · 2023 [cited by applicant]
US 20230351089A1 · Oriordan et al. · 2023 [cited by applicant]
US 20230359804A1 · Oriordan · 2023 [cited by applicant]
US 20240220702A1 · Thulasi et al. · 2024 [cited by applicant]
US 20240288764A1 · Hamouda · 2024 [cited by applicant]
US 20240334611A1 · Thulasi et al. · 2024 [cited by applicant]
CN 107438842A · 2017 [cited by applicant]
CN 111758072A · 2020 [cited by applicant]
CN 113168085A · 2021 [cited by applicant]
CN 113168115A · 2021 [cited by applicant]
EP 3951496A1 · 2022 [cited by applicant]
JP 2004320004A · 2004 [cited by applicant]
JP 2007536581A · 2007 [cited by applicant]
JP 2008122929A · 2008 [cited by applicant]
JP 2012181298A · 2012 [cited by applicant]
JP 2019114295A · 2019 [cited by applicant]
JP 2021509208A · 2021 [cited by applicant]
KR 102170578B1 · 2020 [cited by applicant]
KR 20210010897A · 2021 [cited by applicant]
KR 102377411B1 · 2022 [cited by applicant]
KR 20260035214A · 2026 [cited by applicant]
TW I710763B · 2020 [cited by applicant]
TW 202113501A · 2021 [cited by applicant]
TW 202121050A · 2021 [cited by applicant]
WO 2018125220A1 · 2018 [cited by applicant]
WO 2020193095A1 · 2020 [cited by applicant]
WO 2021041963A1 · 2021 [cited by applicant]
WO 2021043936A1 · 2021 [cited by applicant]
WO 2022086825A1 · 2022 [cited by applicant]
WO 2023141045A2 · 2023 [cited by applicant]
Ajayi, Tutu, et al., “OpenRoad: Toward a Self-Driving, Open-Source Digital Layout Implementation Tool Chain,” Proceedings of Government Microcircuit Applications and Critical Technology Conference, Jan. 1, 2019, 6 pages… [cited by applicant]
Author Unknown, “Boolean operations on polygons,” Wikipedia, Oct. 12, 2019, 3 pages, Wikipedia.com. [cited by applicant]
Author Unknown, “Cadence Virtuoso Layout Suite for Electrically Aware Design,” Cadence, Jun. 2013, 2 pages, Cadence Design Systems, Inc. [cited by applicant]
Author Unknown, “Custom Compiler: Best-in-Class Technology for Advanced-node Custom Design,” Synopsys Datasheet, Oct. 18, 2018, 5 pages, Synopsys, Inc. [cited by applicant]
Author Unknown, “D2S Enables “Stitchless” Full-Chip Inverse Lithography Technology in a Single Day for the Multi-Beam Era,” Press Release, Sep. 16, 2019, 3 pages, D2S, Inc., San Jose, California, USA. [cited by applicant]
Author Unknown, “D2S Unveils Industry's First Mask-Wafer Double Simulation Platform,” Press Release, Sep. 20, 2011, 3 pages, D2S, Inc., San Jose, California, USA. [cited by applicant]
Author Unknown, “Deep reinforcement learning,” Wikipedia, Sep. 21, 2020, 2 pages, Wikipedia.com. [cited by applicant]
Author Unknown, “Design rule checking,” Wikipedia, May 27, 2020, 4 pages, Wikipedia.com. [cited by applicant]
Author Unknown, “Greiner-Hormann clipping algorithm,” Wikipedia, Dec. 5, 2019, 3 pages, Wikipedia.com. [cited by applicant]
Author Unknown, “Marching squares,” Wikipedia, Dec. 30, 2019, 9 pages, Wikipedia.com. [cited by applicant]
Author Unknown, “Multiple patterning,” Wikipedia, Oct. 10, 2020, 22 pages, Wikipedia.com. [cited by applicant]
Author Unknown, “Optical proximity correction,” Wikipedia, Apr. 28, 2019, 5 pages, Wikipedia.com. [cited by applicant]
Author Unknown, “Rasterisation,” Wikipedia, Aug. 21, 2020, 4 pages, Wikipedia.com. [cited by applicant]
Author Unknown, “Sutherland-Hodgman algorithm,” Wikipedia, Feb. 20, 2020, 4 pages, Wikipedia.com. [cited by applicant]
Author Unknown, “TrueMask® DS,” Exact Date Unknown but Before May 2020, 3 pages, D2S, Inc., retrieved from https://design2silicon.com/products/truemask-ds/. [cited by applicant]
Author Unknown, “TrueMask® ILT Backgrounder Stitchless Full-Chip ILT in a Day,” Backgrounder, Sep. 2019, 6 pages, D2S, Inc., San Jose, California, USA. [cited by applicant]
Author Unknown, “TrueMask® ILT,” Exact Date Unknown but Before May 2020, 7 pages, D2S, Inc., retrieved from https://design2silicon.com/products/truemask-ilt/. [cited by applicant]
Cecil, Thomas, et al., “Establishing Fast, Practical, Full-Chip ILT Flows Using Machine Learning,” SPIE Proceedings 11327, Optical Microlithography XXXIII, Mar. 23, 2020, 19 pages, vol. 1132706, SPIE, San Jose, Californ… [cited by applicant]
Chen, Kun-Yuan, et al., “Full-Chip Application of Machine Learning SRAFs on DRAM Case Using Auto Pattern Selection,” SPIE Proceedings 10961, Optical Microlithography XXXII, Oct. 10, 2019, 13 pages, vol. 1096108, SPIE, S… [cited by applicant]
Chen, Tai-Chen, “Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction,” Jun. 2007, 13 pages, IEEE, retrieved from http://cc.ee.ntu.edu.tw/˜ywchang/Papers/tcad07-mgr.pdf. [cited by applicant]
Ibtehaz, Nabil, et al., “MultiResUNet: Rethinking the U-Net Architecture for Multimodal Biomedical Image Segmentation,” Feb. 11, 2019, 25 pages, retrieved from https://arxiv.org/pdf/1902.04049.pdf. [cited by applicant]
Jia, Ningning, et al., “Machine Learning for Inverse Lithography: using stochastic gradient descent for robust photomask synthesis,” Journal of Optics, Apr. 1, 2010, 9 pages, vol. 12, IOP Publishing, retrieved from http… [cited by applicant]
Kwan, Joe, et al., “Applying Machine Learning Techniques to Accelerate Advanced Process Yield Ramp,” Jan. 5, 2021, 29 pages, Siemens Digital Industries Software, Munich, Germany. [cited by applicant]
Lin, Yibo, et al., “Machine Learning for Yield Learning and Optimization,” 2018 IEEE International Test Conference (ITC), Oct. 29-Nov. 1, 2018, 10 pages, IEEE, Phoenix, AZ, USA. [cited by applicant]
Liu, Peng, “Mask Synthesis Using Machine Learning Software and Hardware Platforms,” SPIE Proceedings 11327, Optical Microlithography XXXIII, Mar. 23, 2020, 17 pages, vol. 1132707, SPIE, San Jose, California, USA. [cited by applicant]
Naik, Mehul, “Challenges to Interconnect Scaling at 3nm and Beyond,” Applied Materials, Jun. 14, 2021, 9 pages, Applied Materials, Inc., retrieved from https://www.appliedmaterials.com/us/en/blog/blog-posts/challenges-t… [cited by applicant]
Pang, Linyong (Leo), et al., “Study of Mask and Wafer Co-design That Utilizes a New Extreme SIMD Approach to Computing in Memory Manufacturing: Full-Chip Curvilinear ILT in a Day,” SPIE Proceedings 11148, Photomask Tech… [cited by applicant]
Pang, Linyong, “Inverse Lithography Technology: 30 years from concept to practical, full-chip reality,” Journal of Micro/Nanopatterning, Materials, and Metrology, Aug. 31, 2021, 49 pages, vol. 20(3), SPIE, retrieved fro… [cited by applicant]
Pang, Linyong, et al., “How GPU-Accelerated Simulation Enables Applied Deep Learning for Masks and Wafers,” Photomask Japan 2019: XXVI Symposium on Photomask and Next-Generation Lithography Mask Technology, Apr. 16-18, … [cited by applicant]
Pang, Linyong, et al., “Making Digital Twins using the Deep Learning Kit (DLK),” Photomask Technology 2019, Sep. 15-19, 2019, 13 pages, SPIE, Monterey, California, USA. [cited by applicant]
PCT International Search Report and Written Opinion of Commonly Owned International Patent Application PCT/US2023/010630, mailing date Jun. 27, 2023, 18 pages, International Searching Authority (US). [cited by applicant]
Pradipta, Geraldo, et al., “A Machine Learning Based Parasitic Extraction Tool,” Oct. 31, 2019, 3 pages, University of Minnesota, Minneapolis, Minnesota, USA. [cited by applicant]
Ren, Haoxing (Mark), “Machine Learning and Deep Learning Applications in Design Automation and Practical Issues,” DAC '19: 56th Annual Design Automation Conference 2019, Jun. 2-6, 2019, 55 pages, Association for Computi… [cited by applicant]
Ronneberger, Olaf, et al., “U-Net: Convolutional Networks for Biomedical Image Segmentation,” May 18, 2015, 8 pages, retrieved from https://arxiv.org/pdf/1505.04597.pdf. [cited by applicant]
Shi, Xuelong, et al., “Physics based feature Vector Design: a Critical Step Towards Machine Learning based Inverse Lithography,” SPIE Proceedings 11327, Optical Microlithography XXXIII, Mar. 23, 2020, 8 pages, vol. 1132… [cited by applicant]
Sole, Marc Pons, “Layout Regularity for Design and Manufacturability,” Doctoral Thesis, Jul. 8, 2012, 185 pages, Technical University of Catalonia, Barcelona, Spain. [cited by applicant]
Sperling, Ed, “Design Rule Complexity Rising,” Semiconductor Engineering—Deep Insights for the Tech Industry, Apr. 19, 2018, 16 pages, SMG, retrieved from https://semiengineering.com/design-rule-complexity-rising/. [cited by applicant]
Srivastava, Navin, et al., “Interconnect Challenges for Nanoscale Electronic Circuits,” JOM: The Journal of the Minerals, Metals & Materials Society, Oct. 2004, 2 pages, vol. 56, Issue 10, Silicon Nanoelectronics, retri… [cited by applicant]
Teig, Steven L., “The X architecture: not your father's diagonal wiring,” SLIP '02: Proceedings of the 2002 international workshop on System-level interconnect prediction, Apr. 6, 2002, 5 pages, ACM, retrieved from http… [cited by applicant]
Wang, Shibing, et al., “Efficient Full-Chip SRAF Placement Using Machine Learning for Best Accuracy and Improved Consistency,” SPIE Proceedings 10587, Optical Microlithography XXXI, Mar. 20, 2018, 10 pages, vol. 105870N… [cited by applicant]
Wang, Shibing, et al., “Machine Learning Assisted SRAF Placement for Full Chip,” SPIE Proceedings 10451, Photomask Technology 2017, Oct. 16, 2017, 8 pages, vol. 104510D, SPIE, Monterey, California, USA. [cited by applicant]
Yang, Dingcheng, et al., “CNN-Cap: Effective Convolutional Neural Network Based Capacitance Models for Full-Chip Parasitic Extraction,” Jul. 14, 2021, 9 pages, retrieved from https://arxiv.org/pdf/2107.06511.pdf. [cited by applicant]
Jhaveri, Tejas K., et al., “Maximization of layout printability/manufacturability by extreme layout regularity,” Journal of Micro/Nanolithography, MEMS, and MOEMS, Jul. 1, 2007, 3 pages, vol. 6, Issue 3, SPIE. [cited by applicant]
Jhaveri, Tejas, et al., “Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Apr. 2010, … [cited by applicant]
Dong, Xuan, et al., “Process-Variation-Aware Rule-Based Optical Proximity Correction for Analog Layout Migration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, No. 8, Aug. 1, 2… [cited by applicant]
Elsemary, Ahmed Mounir, et al., “Litho Friendly via insertion with In-Design Auto-Fix flow using Machine Learning” Proceedings of SPIE, vol. 10588, Design-Process-Technology Co-optimization for Manufacturability XII, Ap… [cited by applicant]
Extended European Search Report of Commonly Owned European Patent Application 23743617.5, mailing date Dec. 8, 2025, 10 pages, European Patent Office. [cited by applicant]
Shao, Dongbing, et al., “Incorporating Process Variation Contours in Design Rule Calculation and SRAM Design Optimization”, Proceedings of SPIE, vol. 10962, Design-Process-Technology Co-optimization for Manufacturabilit… [cited by applicant]
Shao, Hao-Chiang, et al., “From IC Layout to Die Photograph: A CNN-Based Data-Driven Approach” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, No. 5, May 2021, pp. 957-970, IEEE. [cited by applicant]
Watanabe, Yuki, et al., “Accurate Lithography Simulation Model based on Deep Learning” Institute of Electronics, Information, and Communication Engineers (IEICE) Technical Report, Nov. 2016, vol. 116, No. 330, pp. 73-78. [cited by applicant]
Kareem, Pervaiz, et. al., “Fast Prediction of Process Variation Band through Machine Learning Models,” Optical Microlithography XXXIV, Feb. 2021, vol. 11613, 8 pages, Proceedings of SPIE—The International Society for Op… [cited by applicant]