Semiconductor device and method of manufacture
Semiconductor devices and methods which utilize a passivation dopant to passivate a gate dielectric layer are provided. The passivation dopant is introduced to the gate dielectric layer through a work function layer using a process such as a soaking method. The passivation dopant is an atom which may help to passivate electrical trapping defects, such as fluorine.
1. A semiconductor device comprising:
a gate dielectric layer over a semiconductor fin;
a first work function layer over the gate dielectric layer, the first work function layer having a first fluorine concentration gradient and a second fluorine concentration gradient opposite the first fluorine concentration gradient; and
a fill material over the first work function layer.
2. The semiconductor device of claim 1 , wherein the first work function layer comprises titanium nitride.
3. The semiconductor device of claim 1 , further comprising an interfacial layer between the gate dielectric layer and the semiconductor fin.
4. The semiconductor device of claim 3 , wherein the gate dielectric layer has a third fluorine concentration gradient.
5. The semiconductor device of claim 4 , wherein the interfacial layer has a fourth fluorine concentration gradient.
6. The semiconductor device of claim 1 , wherein the first work function layer comprises titanium nitride and aluminum.
7. The semiconductor device of claim 1 , wherein the first work function layer comprises tungsten nitride.
8. A semiconductor device comprising:
a semiconductor fin over a semiconductor substrate;
a gate dielectric overlying the semiconductor fin;
a first work function layer overlying the gate dielectric;
fluorine located within the first work function layer, wherein the fluorine has a varying concentration throughout the first work function layer, the fluorine having a maximum concentration located away from any surface of the first work function layer; and
a fill material located over the first work function layer.
9. The semiconductor device of claim 8 , wherein the first work function layer comprises titanium nitride.
10. The semiconductor device of claim 9 , wherein the first work function layer comprises aluminum.
11. The semiconductor device of claim 8 , further comprising an interfacial layer located between the semiconductor fin and the gate dielectric.
12. The semiconductor device of claim 11 , wherein the fluorine extends into both the gate dielectric and the interfacial layer.
13. The semiconductor device of claim 12 , wherein the fluorine has a varying concentration throughout the gate dielectric, the fluorine having a maximum concentration located away from any surface of the gate dielectric.
14. The semiconductor device of claim 13 , wherein the fluorine within the interfacial layer has a maximum concentration adjacent to the gate dielectric.
15. A semiconductor device comprising:
a semiconductor fin;
an interfacial layer over the semiconductor fin;
a gate dielectric layer over the interfacial layer;
a first work function metal layer over the gate dielectric layer, wherein the first work function metal layer has a first decreasing concentration of fluorine and also has a first increasing concentration of fluorine; and
a fill material over the first work function metal layer.
16. The semiconductor device of claim 15 , wherein the first work function metal layer comprises a first layer of a first material and a second layer of a second material different from the first material.
17. The semiconductor device of claim 16 , wherein the first material is titanium nitride and the second material is aluminum.
18. The semiconductor device of claim 15 , wherein the gate dielectric layer comprises hafnium oxide.
19. The semiconductor device of claim 15 , wherein the first work function metal layer comprises titanium nitride.
20. The semiconductor device of claim 15 , wherein the interfacial layer comprises silicon oxide and has a decreasing concentration of fluorine.