Method of forming a stress reduction structure for metal-insulator-metal capacitors
A method and semiconductor device including a substrate having one or more semiconductor devices. In some embodiments, the device further includes a first passivation layer disposed over the one or more semiconductor devices. The device may further include a metal-insulator-metal (MIM) capacitor structure formed over the first passivation layer. In addition, the device may further include a second passivation layer disposed over the MIM capacitor structure. In various examples, a stress-reduction feature is embedded within the second passivation layer. In some embodiments, the stress-reduction feature includes a first nitrogen-containing layer, an oxygen-containing layer disposed over the first nitrogen-containing layer, and a second nitrogen-containing layer disposed over the oxygen containing layer.
1. A method, comprising:
depositing a first passivation layer over a substrate including one or more semiconductor devices;
forming a metal-insulator-metal (MIM) capacitor over the first passivation layer; and
forming a second passivation layer over the MIM capacitor, wherein the forming the second passivation layer includes:
depositing a first dielectric portion of the second passivation layer over the MIM capacitor;
forming a stress-reduction feature of the second passivation layer over the first dielectric portion, wherein the forming the stress-reduction feature includes depositing a first nitrogen-containing layer over the first dielectric portion, depositing an oxygen-containing layer over the first nitrogen-containing layer and depositing a second nitrogen-containing layer over the oxygen-containing layer; and
depositing a second dielectric portion of the second passivation layer over the stress-reduction feature;
wherein the first nitrogen-containing layer has a first thickness, wherein the oxygen-containing layer has a second thickness, wherein the second nitrogen- containing layer has a third thickness, and wherein the second thickness is less than each of the first thickness and the third thickness.
2. The method of claim 1 , wherein prior to the depositing the second dielectric portion of the second passivation layer over the stress-reduction feature, patterning the stress-reduction feature such that the patterned stress-reduction feature remains disposed over the MIM capacitor.
3. The method of claim 2 , wherein a first area of the substrate covered by the patterned stress-reduction feature is substantially equal to or greater than a second area of the substrate covered by the MIM structure.
4. The method of claim 1 , further comprising:
forming a first contact feature and a second contact feature over the second passivation layer, wherein the first contact feature provides electrical contact to a first terminal of the MIM capacitor, and wherein the second contact feature provides electrical contact to a second terminal of the MIM capacitor.
5. The method of claim 1 , wherein the first nitrogen-containing layer and the second nitrogen-containing layer include silicon nitride (SiN), and wherein the oxygen-containing layer includes an oxide layer.
6. The method of claim 1 , further comprising:
prior to depositing the first passivation layer, forming a multi-layer interconnect (MLI) structure at least partially disposed within the substrate; and
depositing the first passivation layer over the MLI structure.
7. The method of claim 6 , further comprising:
forming a contact feature over the second passivation layer, wherein the contact feature is electrically coupled to the MLI structure.
8. The method of claim 7 , further comprising:
forming a third passivation layer over the second passivation layer, wherein the contact feature is disposed within the third passivation layer.
9. The method of claim 1 , wherein a ratio of each of the first thickness and the third thickness to the second thickness is in a range between about 2:1 and about 3:1.
10. A method, comprising:
depositing a first passivation layer over a substrate including an active semiconductor device;
forming a metal-insulator-metal (MIM) structure over the first passivation layer;
after forming the MIM structure, depositing a first dielectric portion over the MIM structure; and
forming a stress-reduction feature over the first dielectric portion, wherein the stress-reduction feature includes a first nitrogen-containing layer, an oxygen-containing layer disposed over the first nitrogen-containing layer, and a second nitrogen-containing layer disposed over the oxygen-containing layer;
wherein the first nitrogen-containing layer has a first thickness, wherein the oxygen-containing layer has a second thickness, wherein the second nitrogen-containing layer has a third thickness, and wherein the second thickness is less than each of the first thickness and the third thickness.
11. The method of claim 10 , further comprising:
depositing a second dielectric portion over the stress-reduction feature.
12. The method of claim 11 , wherein the first dielectric portion and the second dielectric portion provide a second passivation layer, and wherein the stress-reduction feature is embedded within the second passivation layer.
13. The method of claim 10 , wherein the first nitrogen-containing layer and the second nitrogen-containing layer include silicon nitride (SiN), and wherein the oxygen-containing layer includes an oxide layer.
14. The method of claim 10 , further comprising:
after forming the stress-reduction feature, patterning the stress-reduction feature to form a patterned stress-reduction feature, wherein the patterned stress-reduction feature remains disposed over the MIM structure.
15. The method of claim 14 , wherein a first area of the substrate covered by the patterned stress-reduction feature is substantially equal to or greater than a second area of the substrate covered by the MIM structure.
16. The method of claim 10 , wherein a ratio of each of the first thickness and the third thickness to the second thickness is in a range between about 2:1 and about 3:1.
17. A method, comprising:
forming a metal-insulator-metal (MIM) capacitor over a substrate;
forming a passivation layer over the MIM capacitor, wherein the passivation layer has an embedded stress-reduction feature, wherein the embedded stress-reduction feature includes a nitrogen-oxygen-nitrogen (NON) multi-layer structure; and
after forming the passivation layer, forming a first contact feature and a second contact feature over the passivation layer, wherein the first contact feature provides electrical contact to a first terminal of the MIM capacitor, and wherein the second contact feature provides electrical contact to a second terminal of the MIM capacitor;
wherein the NON multi-layer structure includes an oxide layer interposing a first silicon nitride (SiN) layer and a second SiN layer; and
wherein the first SiN layer has a first thickness, wherein the oxide layer has a second thickness, wherein the second SiN layer has a third thickness, and wherein the second thickness is less than each of the first thickness and the third thickness.
18. The method of claim 17 , wherein the forming the passivation layer further comprises:
depositing a first dielectric portion over the MIM capacitor;
forming the embedded stress-reduction feature over the first dielectric portion; and
depositing a second dielectric portion over the embedded stress-reduction feature.
19. The method of claim 17 , further comprising:
prior to forming the MIM capacitor, depositing a separate passivation layer over the substrate; and
forming the MIM capacitor over the separate passivation layer.
20. The method of claim 17 , wherein a ratio of each of the first thickness and the third thickness to the second thickness is in a range between about 2:1 and about 3:1.