Vertical channel transistor including a graphene insertion layer beweeen a source/drain electrode and a channel pattern
A vertical channel transistor includes a first source/drain electrode; a second source/drain electrode spaced apart from the first source/drain electrode in a first direction; a first channel pattern between the first source/drain electrode and the second source/drain electrode; a first gate electrode on a side surface of the first channel pattern; a first gate insulation layer between the first channel pattern and the first gate electrode; and a first graphene insertion layer between the first source/drain electrode and the first channel pattern.
1. A vertical channel transistor comprising:
a first source/drain electrode;
a second source/drain electrode spaced apart from the first source/drain electrode in a first direction;
a first channel pattern between a surface of the first source/drain electrode and a surface of the second source/drain electrode facing the surface of the first source/drain electrode;
a first gate electrode on a side surface of the first channel pattern;
a first gate insulation layer between the first channel pattern and the first gate electrode;
a first graphene insertion layer between the first source/drain electrode and the first channel pattern; and
a second graphene insertion layer between the second source/drain electrode and the first channel pattern, wherein the second graphene insertion layer fully surrounds the second source/drain electrode.
2. The vertical channel transistor of claim 1 ,
wherein a region of the surface of the first source/drain electrode faces a surface of the first gate insulation layer in the first direction, and
the first graphene insertion layer extends in a second direction between the first gate insulation layer and the first source/drain electrode, and
the second direction crosses the first direction.
3. The vertical channel transistor of claim 1 , further comprising:
a first additional source/drain electrode between the first graphene insertion layer and the first channel pattern,
wherein the first source/drain electrode and the first additional source/drain electrode comprise different materials from each other.
4. The vertical channel transistor of claim 3 ,
wherein a region of a surface of the first additional source/drain electrode faces a surface of the first gate insulation layer in the first direction, and
the first additional source/drain electrode directly contacts the first gate insulation layer.
5. The vertical channel transistor of claim 1 , wherein
a lower surface of the first gate insulation layer is coplanar with a lower surface of the first channel pattern.
6. The vertical channel transistor of claim 1 ,
wherein a thickness of at least one of the first graphene insertion layer and the second graphene insertion layer is about 0.34 nanometers (nm) to about 3 nm.
7. The vertical channel transistor of claim 1 ,
wherein at least one of the first graphene insertion layer and the second graphene insertion layer comprises crystals having domain sizes from about 0.5 nm to about 100 nm.
8. The vertical channel transistor of claim 1 ,
wherein a ratio of carbon atoms having a sp2 bonding structure with respect to entire carbon atoms in at least one of the first graphene insertion layer and the second graphene insertion layer is 50% to 99%.
9. The vertical channel transistor of claim 1 ,
wherein at least one of the first graphene insertion layer and the second graphene insertion layer has a density of about 1.6 g/cc to about 2.1 g/cc.
10. The vertical channel transistor of claim 1 ,
wherein the first source/drain electrode includes a metal or a metal alloy.
11. The vertical channel transistor of claim 1 ,
wherein the first gate insulation layer surrounds side surfaces of the first channel pattern, and
the first gate electrode extends along the first gate insulation layer and surrounds the first channel pattern.
12. The vertical channel transistor of claim 1 , further comprising:
a second gate electrode opposite the first gate electrode across the first channel pattern; and
a second gate insulation layer between the second gate electrode and the first channel pattern.
13. The vertical channel transistor of claim 1 , further comprising:
a passivation layer on the first source/drain electrode, the passivation layer covering the second source/drain electrode,
wherein a region of the first graphene insertion layer is between the passivation layer and the first source/drain electrode.
14. The vertical channel transistor of claim 13 , further comprising:
a second graphene insertion layer between the second source/drain electrode and the first channel pattern,
wherein a region of the second graphene insertion layer is between the passivation layer and the second source/drain electrode.
15. A vertical channel transistor comprising:
a first source/drain electrode;
a second source/drain electrode spaced apart from the first source/drain electrode in a first direction;
a first channel pattern between the first source/drain electrode and the second source/drain electrode;
a first gate electrode on a side surface of the first channel pattern;
a first gate insulation layer between the first channel pattern and the first gate electrode;
a first graphene insertion layer between the first source/drain electrode and the first channel pattern;
a second channel pattern provided opposite the first channel pattern across first gate electrode; and
a second gate insulation layer between the first gate electrode and the second channel pattern,
wherein the first channel pattern and the second channel pattern are in a region where the first source/drain electrode and the second source/drain electrode face each other in the first direction.
16. The vertical channel transistor of claim 15 , further comprising:
a second graphene insertion layer between the second source/drain electrode and the first channel pattern;
a first insulation pattern between the first gate electrode and the first graphene insertion layer;
a second insulation pattern between the first gate electrode and the second graphene insertion layer; and
a third channel pattern between the second graphene insertion layer and the second insulation pattern,
wherein the first channel pattern, the second channel pattern, and the third channel pattern constitute a single structure.
17. A vertical channel transistor comprising:
a first source/drain electrode;
a channel pattern on the first source/drain electrode;
a second source/drain electrode on the channel pattern, the second source/drain electrode being spaced apart from the first source/drain electrode in a first direction;
a first graphene insertion layer between the first source/drain electrode and the channel pattern;
a gate electrode over the first source/drain electrode and spaced apart from the first source/drain electrode in the first direction; and
a gate insulation layer on a sidewall of the channel pattern between the gate electrode and channel pattern,
wherein the gate electrode is between the first source/drain electrode and a region of the channel pattern.
18. The vertical channel transistor of claim 17 , wherein
the channel pattern is between the first source/drain electrode and the second source/drain electrode.
19. The vertical channel transistor of claim 17 , further comprising:
a second graphene insertion layer on the second source/drain electrode, wherein
a surface of the second graphene insertion layer faces a surface of the first source/drain electrode.