Semiconductor device and manufacturing method therefor

1. A method for manufacturing a semiconductor device, comprising:

providing a substrate structure comprising a substrate and a first material layer on the substrate, wherein a recess is formed in the substrate and the first material layer comprises a nanowire spanning and suspended above the recess;

forming a base layer on the substrate structure, wherein the base layer comprises at least a first portion covering an exposed surface of the nanowire and a second portion covering an exposed surface of the recess;

selectively growing a graphene layer on the base layer;

forming a second dielectric layer on the graphene layer;

forming an electrode material layer on the substrate structure to cover the second dielectric layer;

partially removing the electrode material layer, the second dielectric layer, and the graphene layer so as to define an area of an active region wherein at least a portion of a stack layer of the electrode material layer, the second dielectric layer, and the graphene layer on the nanowire remains and is within the active region; and

forming a gate by etching at least a portion of the stack layer remaining within the active region to at least the second dielectric layer so as to form a gate structure surrounding an intermediate portion of the nanowire, wherein the gate structure comprises a portion of the electrode material layer and the second dielectric layer.

2. The method according to claim 1 , further comprising:

after defining the gate, removing portions of the graphene layer and the second dielectric layer which are on a surface of the recess.

3. The method according to claim 1 , wherein defining the active region comprises:

forming a patterned mask on the electrode material layer, the patterned mask shielding at least a portion of the nanowire; and

removing, by using the patterned mask, portions of the electrode material layer, the second dielectric layer, and the graphene layer not shielded by the patterned mask.

4. The method according to claim 3 , wherein the patterned mask further shields at least a portion of the recess.

5. The method according to claim 3 , wherein

the first material layer further comprises a portion above the first dielectric layer at two ends of the recess bonded to the portion of the first material layer forming the nanowire; and

the patterned mask shields the nanowire, and further shields at least a portion of the first material layer that is bonded to the nanowire.

6. The method according to claim 5 further comprising:

forming a fourth dielectric layer to cover at least the substrate structure and the area of the active region;

forming a hole through the fourth dielectric layer, the second dielectric layer, and the graphene layer to the at least a portion of the first material layer;

forming an insulating material layer on a side wall of the hole; and

filling the hole with a conductive material after forming the insulating material layer on the side wall of the hole so as to form a contact component to the at least a portion of the first material layer,

wherein the insulating material layer electrically isolates the graphene layer from the contact component.

7. The method according to claim 1 , wherein:

the substrate comprises a substrate layer and a first dielectric layer on the substrate layer;

the first material layer is on the first dielectric layer;

the recess is formed in the first dielectric layer; and

wherein providing a substrate structure comprises:

providing an initial substrate structure comprising the substrate and the first material layer on the first dielectric layer of the substrate;

patterning the first material layer to define a region covering the nanowire and two sides of the nanowire along the length direction of the nanowire; and

removing at least upper portions of the first dielectric layer of the defined region to form the recess.

8. The method according to claim 7 , wherein the recess further extends through the first dielectric layer into the substrate layer.

9. The method according to claim 1 , wherein

the graphene layer comprises a first portion on a surface of the first portion of the base layer, and a second portion on a surface of the second portion of the base layer;

the second dielectric layer comprises a first portion on a surface of the first portion of the graphene layer, and a second portion on a surface of the second portion of the graphene layer; and

the electrode material layer is further formed to fill a space below the nanowire and between the first portion of the second dielectric layer and the second portion of the second dielectric layer when forming the electrode material layer.

10. The method according to claim 1 , wherein:

the first material layer comprises polysilicon, doped polysilicon, or silicon germanium;

the base layer comprises an oxide of aluminum;

the first dielectric layer comprises an oxide of silicon; and

the second dielectric layer comprises boron nitride, an oxide of silicon, an oxide of hafnium, an oxide of aluminum, or a nitride of aluminum.

11. The method according to claim 1 , wherein

the base layer comprises an oxide of aluminum; and

selectively growing the graphene layer on the base layer comprises selectively growing the graphene layer at a temperature of 900-1000° C. by a chemical vapor deposition process using methane and hydrogen.

12. The method according to claim 1 , wherein

the nanowire comprises doped polysilicon; and

the portion of the electrode material layer in the gate structure is used as a first gate, and the nanowire is used as a second gate.

13. The method according to claim 1 , wherein defining the gate comprises:

forming a third dielectric layer to cover at least the substrate structure and the area of the active region; and

etching, by using a patterned mask defining a gate area, a portion of the third dielectric layer outside the gate area and at least a portion of the stack layer within the active region but outside the gate area to at least the second dielectric layer so as to form a gate structure surrounding an intermediate portion of the nanowire, wherein the gate structure comprises a portion of the electrode material layer and the second dielectric layer.

14. The method according to claim 1 , after the forming the gate, further comprising:

forming a fourth dielectric layer to cover at least the substrate structure and the area of the active region;

forming a hole through the fourth dielectric layer and the second dielectric layer to the graphene layer, the hole being separated from the gate structure; and

filling the hole with a conductive material, so as to form a contact component to the graphene layer.

15. The method according to claim 1 , further comprising:

forming a fourth dielectric layer to cover at least the substrate structure and the area of the active region;

forming a hole through the fourth dielectric layer, the second dielectric layer, and the graphene layer to the first material layer;

forming an insulating material layer on a side wall of the hole; and

filling the hole with a conductive material after forming the insulating material layer on the side wall of the hole so as to form a contact component to the first material layer.