Thin film structure and electronic device including two-dimensional material
Provided is a thin film structure including a substrate, a metal layer on the substrate and spaced apart from the substrate, and a two-dimensional material layer between the substrate and the metal layer. The two-dimensional material layer may be configured to limit and/or block an electron transfer between the substrate and the metal layer. A resistivity of a metal layer on the two-dimensional material layer may be lowered by the two-dimensional material layer.
1. A thin film structure comprising:
a substrate;
a metal layer on the substrate and spaced apart from the substrate; and
a two-dimensional material layer between the substrate and the metal layer, the two-dimensional material layer being configured to block an electron transfer between the metal layer and the substrate, wherein
the two-dimensional material layer covers a top surface of the metal layer, a side surface of the metal layer, and a lower surface of the metal layer.
2. The thin film structure of claim 1 , wherein a resistivity of the metal layer is decreased by the two-dimensional material layer.
3. The thin film structure of claim 1 , wherein the two-dimensional material layer includes a two-dimensional insulator.
4. The thin film structure of claim 3 , wherein the two-dimensional insulator includes BN, MnO 2 , MoO 3 , GaSe, Ga 2 N 3 , or As 2 S 3 .
5. The thin film structure of claim 3 , further comprising:
a graphene layer between the two-dimensional material layer and the metal layer.
6. The thin film structure of claim 5 , wherein
the metal layer is directly on the graphene layer.
7. The thin film structure of claim 1 , wherein the metal layer includes W, Mo, Co, Ru, Rh, or Ir.
8. The thin film structure of claim 1 , wherein
the metal layer is directly on the two-dimensional material layer.
9. An electronic device comprising:
a channel layer including a semiconductor material;
a gate electrode on the channel layer and spaced apart from the channel layer; and
a two-dimensional material layer between the channel layer and the gate electrode, the two-dimensional material layer being configured to block an electron transfer between the gate electrode and the channel layer; and
a charge trap layer between the channel layer and the two-dimensional material layer, the charge trap layer including a trap layer and a tunneling oxide layer.
10. The electronic device of claim 9 , wherein the two-dimensional material layer includes a two-dimensional insulator.
11. The electronic device of claim 10 , wherein the two-dimensional insulator includes BN, MnO 2 , MoO 3 , GaSe, Ga 2 N 3 , or As 2 S 3 .
12. The electronic device of claim 9 , further comprising:
a graphene layer between the two-dimensional material layer and the gate electrode.
13. The thin film structure of claim 1 , further comprising:
a charge trap layer between the substrate and the two-dimensional material layer, wherein
the charge trap layer includes a trap layer and a tunneling oxide layer.
14. The electronic device of claim 9 , wherein
the two-dimensional material layer is between the channel layer and a side surface of the gate electrode.
15. The electronic device of claim 9 , wherein the channel layer includes poly-Si.
16. The electronic device of claim 9 , comprising:
a plurality of memory cells that each include the channel layer, the charge trap layer, the two-dimensional material layer, and the gate electrode,
wherein the plurality of memory cells are arranged in a direction perpendicular to a direction in which the channel layer, the charge trap layer, the two-dimensional material layer, and the gate electrode are arranged.
17. The electronic device of claim 16 , further comprising:
a column-shaped insulator,
wherein the channel layer, the charge trap layer, the two-dimensional material layer, and the gate electrode surround a lateral side of the column-shaped insulator
the channel layer is between the lateral side of the column-shaped insulator and the two-dimensional material layer, and
the charge trap layer is between the channel layer and the two-dimensional material layer.
18. The electronic device of claim 17 , further comprising:
a graphene layer between the gate electrode and the two-dimensional material layer.
19. An electronic apparatus comprising:
a memory device including a plurality of memory cells; and
a memory controller configured to control the memory device,
wherein each of the plurality of memory cells comprises a channel layer, a gate electrode, a two-dimensional material layer, and a memory layer,
the channel layer includes a semiconductor material,
the gate electrode is on the channel layer and spaced apart from the channel layer,
the two-dimensional material layer is between the channel layer and the gate electrode,
the two-dimensional material layer is configured to block an electron transfer between the gate electrode and the channel layer, and
the memory layer is between the channel layer and the gate electrode.
20. The electronic apparatus of claim 19 , wherein the memory layer includes a charge trap layer or a ferroelectric layer.