Vertical nonvolatile memory device including gate electrodes with metal-doped graphene
A vertical nonvolatile memory device may include a channel layer extending in a first direction; a plurality of gate electrodes and a plurality of spacers each extending in a second direction crossing the first direction, the plurality of gate electrodes and the plurality of spacers being alternately arranged with each other in the first direction; and a gate insulating layer extending in the first direction between the channel layer and the plurality of gate electrodes. Each of the plurality of gate electrodes may include a metal-doped graphene.
1 . A nonvolatile memory device comprising:
a channel layer extending in a first direction;
a plurality of gate electrodes and a plurality of spacers each extending in a second direction crossing the first direction, the plurality of gate electrodes and the plurality of spacers being alternately arranged with each other in the first direction; and
a gate insulating layer extending in the first direction between the channel layer and the plurality of gate electrodes,
wherein each of the plurality of gate electrodes includes a metal-doped graphene,
the metal-doped graphene includes a metal particle, and
the metal particle includes at least one of Ru, Ti, Pt, Ta, Rh, Ir, and Co.
2 . The nonvolatile memory device of claim 1 , wherein
a ratio of the metal particle to carbon in the metal-doped graphene is about 1 atomic percent (at) % to about 50 at %.
3 . The nonvolatile memory device of claim 1 , wherein a ratio of carbon having an sp 2 bonding structure to total carbon in the metal-doped graphene is about 50% to about 99%.
4 . The nonvolatile memory device of claim 1 , wherein the metal-doped graphene includes intrinsic graphene or nanocrystalline graphene.
5 . The nonvolatile memory device of claim 1 , wherein
the metal-doped graphene includes nanocrystalline graphene, and
the nanocrystalline graphene includes crystals having a size of about 0.5 nm to about 500 nm.
6 . The nonvolatile memory device of claim 1 , wherein a work function of the metal-doped graphene is greater than about 4.7 eV.
7 . The nonvolatile memory device of claim 6 , wherein the work function of the metal-doped graphene is greater than about 4.9 eV.
8 . The nonvolatile memory device of claim 1 , wherein the gate insulating layer includes:
a diffusion barrier layer between the channel layer and the plurality of gate electrodes;
a charge blocking layer between the channel layer and the diffusion barrier layer;
a charge trap layer between the channel layer and the charge blocking layer; and
a tunneling dielectric layer between the channel layer and the charge trap layer.
9 . The nonvolatile memory device of claim 8 , wherein the diffusion barrier layer, the charge blocking layer, the charge trap layer, and the tunneling dielectric layer extend in the first direction along a surface of the channel layer.
10 . The nonvolatile memory device of claim 8 , wherein
the charge blocking layer, the charge trap layer, and the tunneling dielectric layer extend in the first direction along a surface of the channel layer,
the diffusion barrier layer includes a first portion and a second portion,
the first portion extends in the first direction along the surface of the channel layer,
the second portion extends in the second direction, and
the second portion covers an upper surface of each of the plurality of gate electrodes and a lower surface of each of the plurality of gate electrodes.
11 . The nonvolatile memory device of claim 8 , wherein the diffusion barrier layer and the charge blocking layer are integrated in a single layer including hexagonal boron nitride (h-BN).
12 . The nonvolatile memory device of claim 8 , wherein
the gate insulating layer includes a hexagonal boron nitride (h-BN) layer between the channel layer and the plurality of gate electrodes, a charge trap layer between the channel layer and the h-BN layer, and a tunneling dielectric layer between the channel layer and the charge trap layer.
13 . The nonvolatile memory device of claim 12 , wherein the h-BN layer, the charge trap layer, and the tunneling dielectric layer extend in the first direction along a surface of the channel layer.
14 . The nonvolatile memory device of claim 12 , wherein
the charge trap layer and the tunneling dielectric layer extend in the first direction along a surface of the channel layer, and
the h-BN layer includes a portion extending in the first direction along the surface of the channel layer and a portion extending in the second direction to cover an upper surface and a lower surface of each of the plurality of gate electrodes.
15 . The nonvolatile memory device of claim 12 , wherein the h-BN layer, the charge trap layer, and the tunneling dielectric layer each include a portion extending in the first direction along a surface of the channel layer and a portion extending in the second direction to cover an upper surface and a lower surface of each of the plurality of gate electrodes.
16 . The nonvolatile memory device of claim 15 , wherein a side surface of each of the plurality of spacers directly contacts the surface of the channel layer.
17 . A neuromorphic apparatus comprising:
a processing circuit; and
a memory system, wherein
the memory system includes the nonvolatile memory device of claim 1 and a memory controller configured to perform a control operation on the nonvolatile memory device.
18 . A nonvolatile memory device comprising:
a channel layer extending in a first direction;
a plurality of gate electrodes each extending in a second direction crossing the first direction, the plurality of gate electrodes spaced apart from each other in the first direction along a sidewall of the channel layer; and
a gate insulating layer between the channel layer and the plurality of gate electrodes,
wherein each of the plurality of gate electrodes includes a metal-doped graphene,
the metal-doped graphene includes a metal particle, and
the metal particle includes at least one of Ru, Ti, Pt, Ta, Rh, Ir, and Co.
19 . The nonvolatile memory device of claim 18 , wherein
the gate insulating layer includes a charge trap layer spaced apart from the channel layer and the plurality of gate electrodes.
20 . The nonvolatile memory device of claim 19 , wherein
the gate insulating layer includes a tunneling dielectric layer between the channel layer and the charge trap layer.
21 . The nonvolatile memory device of claim 19 , wherein
the gate insulating layer includes a hexagonal boron nitride (h-BN) layer between the charge trap layer and the plurality of gate electrodes.
22 . The nonvolatile memory device of claim 19 , wherein
the gate insulating layer includes a diffusion barrier layer between the charge trap layer and the plurality of gate electrodes, and
the gate insulating layer includes a charge blocking layer between the charge trap layer and the diffusion barrier layer.