IP Library › Granted Patent US 12,648,211
Granted Patent B2
US 12,648,211 · App. 18/151,775 · Granted Jun 2, 2026

Semiconductor device including metal-2 dimensional material-semiconductor junction

Inventors: Keunwook Shin (Yongin-si, KR); Eunkyu Lee (Suwon-si, KR); Changseok Lee (Suwon-si, KR); Changhyun Kim (Seoul, KR); Kyung-Eun Byun (Seongnam-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H10D64/62
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Quick Facts
Patent No.
US 12,648,211
App. No.
18/151,775
Granted
Jun 2, 2026
Kind
B2
Abstract

A semiconductor device may include a first semiconductor layer including a first semiconductor material; a metal layer facing the first semiconductor layer and having conductivity; a 2D material layer between the first semiconductor layer and the metal layer; and a second semiconductor layer between the first semiconductor layer and the 2D material layer. The second semiconductor layer may include a second semiconductor material different from the first semiconductor material. The second semiconductor layer and the 2D material layer may be in direct contact with each other. The second semiconductor material may include germanium.

Claims (75)

1 . A semiconductor device comprising:

a first semiconductor layer including a first semiconductor material;

a metal layer facing the first semiconductor layer, the metal layer having conductivity;

a two-dimensional (2D) material layer between the first semiconductor layer and the metal layer; and

a second semiconductor layer between the first semiconductor layer and the 2D material layer, the second semiconductor layer including a second semiconductor material different from the first semiconductor material, wherein

the second semiconductor layer and the 2D material layer are in direct contact with each other, and

the second semiconductor material includes germanium.

2 . The semiconductor device of claim 1 , wherein,

the first semiconductor material is represented by A,

the first semiconductor layer is represented by A 1-x Ge x , and

the second semiconductor layer is represented by A 1-y Ge y , where 0≤x<1, 0<y≤1, and x<y.

3 . The semiconductor device of claim 1 , wherein

an amount of germanium in the second semiconductor layer is in a range of about 50 at % to 100 at %.

4 . The semiconductor device of claim 1 , wherein

the first semiconductor material includes silicon, wherein

the first semiconductor layer includes Si 1-x Ge x , and

the second semiconductor layer includes Si 1-y Ge y , where 0≤x<1, 0<y≤1, and x<y.

5 . The semiconductor device of claim 1 , wherein a thickness of the second semiconductor layer is in a range of about 1 nm to about 1 μm.

6 . The semiconductor device of claim 1 , wherein the 2D material layer includes intrinsic graphene or nanocrystalline graphene.

7 . The semiconductor device of claim 6 , wherein

the 2D material layer includes the nanocrystalline graphene,

a ratio of carbon having an sp 2 bond structure to total carbon of the nanocrystalline graphene is in a range of about 50% to about 99%,

the 2D material layer includes the nanocrystalline graphene,

the nanocrystalline graphene includes crystals having a size in a range of about 0.5 nm to about 500 nm,

the 2D material layer includes the nanocrystalline graphene,

the nanocrystalline graphene includes hydrogen in a range of about 1 at % to about 20 at %,

the 2D material layer includes the nanocrystalline graphene, and

the nanocrystalline graphene has a density in a range of about 1.6 g/cc to about 2.1 g/cc.

8 . The semiconductor device of claim 1 , further comprising:

a channel region doped a first conductivity type;

a gate insulating layer on the channel region; and

a gate electrode on the gate insulating layer, wherein

the first semiconductor layer includes a source region and a drain region, the source region and the drain region being doped a second conductivity type that is electrically opposite the first conductivity type, and

the source region and the drain region are separated from each other with the channel region therebetween.

9 . The semiconductor device of claim 8 , wherein

the second semiconductor layer includes a first germanium-including semiconductor layer on the source region and a second germanium-including semiconductor layer on the drain region,

the first germanium-including semiconductor layer and the second germanium-including semiconductor layer are separated from each other,

the first germanium-including semiconductor layer and the second germanium-including semiconductor layer are doped the second conductivity type,

the 2D material layer includes a first 2D material layer on the first germanium-including semiconductor layer and a second 2D material layer on the second germanium-including semiconductor layer,

a lower surface of the first germanium-including semiconductor layer is in direct contact with the source region,

an upper surface of the first germanium-including semiconductor layer is in direct contact with the first 2D material layer,

a lower surface of the second germanium-including semiconductor layer is in direct contact with the drain region, and

an upper surface of the second germanium-including semiconductor layer is in direct contact with the second 2D material layer.

10 . The semiconductor device of claim 1 , further comprising:

a gate electrode; and

a gate insulating layer on the gate electrode,

wherein the first semiconductor layer includes a channel layer on the gate insulating layer.

11 . The semiconductor device of claim 10 , wherein the metal layer includes:

a source electrode facing a first side surface of the channel layer; and

a drain electrode facing a second side surface of the channel layer, wherein

the 2D material layer includes a first 2D material layer and a second 2D material layer,

the first 2D material layer is between the source electrode and the first side surface of the channel layer,

the second 2D material layer is between the drain electrode and the second side surface of the channel layer, and

the second semiconductor layer includes a first germanium-including semiconductor layer and a second germanium-including semiconductor layer,

the first germanium-including semiconductor layer is between the first 2D material layer and the first side surface of the channel layer, and

the second germanium-including semiconductor layer is between the second 2D material layer and the second side surface of the channel layer.

12 . The semiconductor device of claim 11 , wherein

the first 2D material layer and the first germanium-including semiconductor layer are bent and extend from the first side surface of the channel layer to a first region of an upper surface of the channel layer, and

the second 2D material layer and the second germanium-including semiconductor layer are bent and extend from the second side surface of the channel layer to a second region of the upper surface of the channel layer.

13 . The semiconductor device of claim 1 , further comprising:

a gate insulating layer; and

a gate electrode on the gate insulating layer, wherein

the first semiconductor layer includes a channel layer, and the gate insulating layer on an upper surface of the channel layer.

14 . The semiconductor device of claim 13 , wherein

the second semiconductor layer includes a first germanium-including semiconductor layer on the upper surface of the channel layer and a second germanium-including semiconductor layer on the upper surface of the channel layer,

the first germanium-including semiconductor layer and the second germanium-including semiconductor layer are separated from each other, and

the gate insulating layer is between the first germanium-including semiconductor layer and the second germanium-including semiconductor layer.

15 . The semiconductor device of claim 14 , wherein

the 2D material layer includes a first 2D material layer on the first germanium-including semiconductor layer and a second 2D material layer on the second germanium-including semiconductor layer, and

the metal layer includes a source electrode on the first 2D material layer and a drain electrode on the second 2D material layer.

16 . The semiconductor device of claim 15 , wherein

a lower surface of the first germanium-including semiconductor layer is in direct contact with the channel layer,

an upper surface of the first germanium-including semiconductor layer is in direct contact with the first 2D material layer,

a lower surface of the second germanium-including semiconductor layer is in direct contact with the channel layer, and

an upper surface of the second germanium-including semiconductor layer is in direct contact with the second 2D material layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2023
From: SHIN, KEUNWOOK; LEE, EUNKYU; LEE, CHANGSEOK; KIM, CHANGHYUN; BYUN, KYUNG-EUN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 062370/0061 →
Priority Claims (1)
KR 10-2022-0051030 · Apr 25, 2022 · national
Continuity (1)
Related Publication 20230343846A1 · Oct 26, 2023
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