Semiconductor package and method of fabricating the same
Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises semiconductor chips stacked on a substrate and including first and second pads on top surfaces thereof, and bonding wires connecting the first and second pads to the substrate. The semiconductor chips alternately protrude in a first direction and its opposite direction. The semiconductor chip has a first lateral surface spaced apart from another semiconductor chip. The top surface of the semiconductor chip is provided thereon with a first arrangement line extending along the first lateral surface and with second arrangement lines extending from opposite ends of the first arrangement line. Wherein as a distance between the first and second arrangement lines increases, a distance between the second arrangement lines and the first lateral surface increases. The first pads are arranged along the first arrangement line. The second pads are arranged along the second arrangement lines.
1. A semiconductor package, comprising:
a substrate;
a plurality of semiconductor chips stacked on the substrate and each of the plurality of semiconductor chips including a plurality of first pads and a plurality of second pads on a top surface thereof; and
a plurality of bonding wires that connect the plurality of first pads and the plurality of second pads of the plurality of semiconductor chips to the substrate,
wherein the plurality of semiconductor chips each protrude relative to adjacent ones of the plurality of semiconductor chips alternately in a first direction and a direction opposite to the first direction, and protruding distances of the plurality of semiconductor chips being same as each other,
wherein the plurality of semiconductor chips each have a first lateral surface spaced apart from another of the plurality of semiconductor chips in overlying or underlying contact therewith,
wherein the top surface of each of the plurality of semiconductor chips is provided thereon with,
a first arrangement line that extends along the first lateral surface; and
a plurality of second arrangement lines that extend from opposite ends of the first arrangement line, wherein as the second arrangement lines increase in distance from the first arrangement line, the second arrangement lines increase in distance from the first lateral surface,
wherein the plurality of first pads are arranged along the first arrangement line, and
wherein the plurality of second pads are arranged along the second arrangement lines.
2. The semiconductor package of claim 1 , wherein
the first arrangement line is a straight line parallel to the first lateral surface, and
the second arrangement lines are straight lines that are inclined at 45 degrees relative to the first lateral surface.
3. The semiconductor package of claim 1 , wherein an increase in distance between the substrate and the plurality of semiconductor chips includes a reduction in length of the first arrangement line and an increase in length of each of the second arrangement lines.
4. The semiconductor package of claim 1 , wherein
the top surface of each of the semiconductor chips has a plurality of chamfer regions defined by the second arrangement lines, the first lateral surface, and a plurality of second lateral surfaces in contact with the first lateral surface, and
no pad is provided on the chamfer regions.
5. The semiconductor package of claim 1 , wherein each of the plurality of second pads of each of the plurality of semiconductor chips has a linear shape that extends toward the first lateral surface.
6. The semiconductor package of claim 5 , wherein as a distance between the substrate and the plurality of semiconductor chips increases, a distance between the first lateral surface and bonding positions of the bonding wires to the plurality of second pads increases.
7. The semiconductor package of claim 1 , wherein
each of the plurality of semiconductor chips further includes a plurality of dummy pads arranged in a second direction toward the first lateral surface and away from the plurality of second pads, and
a single pad group is constituted by one of the plurality of second pads and at least one of the plurality of dummy pads, the at least one dummy pad being positioned in the second direction of the one second pad.
8. The semiconductor package of claim 7 , wherein
the bonding wire is bonded to one selected from the plurality of dummy pads and the one second pad of the pad group, and
wherein as a distance between the substrate and the plurality of semiconductor chips increases, a distance between the first lateral surface and a bonding position of the bonding wire to the one dummy pad and the one second pad of the pad group increases.
9. The semiconductor package of claim 1 , wherein
the plurality of semiconductor chips include a plurality of first semiconductor chips and a plurality of second semiconductor chips that are alternately stacked with each other on the substrate,
wherein the first lateral surfaces of the plurality of first semiconductor chips are on a same first plane, and
the first lateral surfaces of the plurality of second semiconductor chips are on a same second plane.
10. The semiconductor package of claim 9 , wherein
the plurality of semiconductor chips are the same, and
planar shapes of the plurality of first semiconductor chips are symmetric in the first direction to planar shapes of the plurality of second semiconductor chips.