Load matching for a current-steering digital-to-analog converter
Certain aspects of the present disclosure are directed towards a digital-to-analog converter (DAC) system. The DAC system generally includes a first driver and a plurality of current-steering cells. A first current-steering cell of the plurality of current-steering cells includes: a first current source coupled to a first current-steering transistor and a second current-steering transistor, wherein a gate of the first current-steering transistor and a gate of the second current-steering transistor are coupled to a first output and a second output of the first driver, respectively; a first transistor having a source coupled to a current source path and a drain coupled to a reference potential node; and a second transistor having a source coupled to the current source path and a drain coupled to the reference potential node.
1. A digital-to-analog converter (DAC) system, comprising:
a first driver; and
a plurality of current-steering cells, wherein a first current-steering cell of the plurality of current-steering cells comprises:
a second current source configured to provide a second current, a first portion of the second current provided by a first current source and a second portion of the second current provided to a second current-steering cell of the plurality of current-steering cells;
the first current source coupled to a first current-steering transistor and a second current-steering transistor, wherein a gate of the first current-steering transistor and a gate of the second current-steering transistor are coupled to a first output and a second output of the first driver, respectively;
a first transistor having a source coupled to a current source path, a drain coupled to a reference potential node, and a gate coupled to the first output of the first driver;
a second transistor having a source coupled to the current source path, a drain coupled to the reference potential node, and a gate coupled to the second output of the first driver; and
a third transistor configured to receive a first current at a source of the third transistor, a drain of the third transistor being coupled to the sources of the first transistor and the second transistor.
2. The DAC system of claim 1 , wherein the first current-steering cell further comprises a fourth transistor coupled between the first current source and a current-steering node, the current-steering node being coupled to sources of the first current-steering transistor and the second current-steering transistor.
3. The DAC system of claim 2 , wherein a gate of the fourth transistor is coupled to a gate of the third transistor.
4. The DAC system of claim 1 , wherein:
a drain of the first current-steering transistor is coupled to a first output of the DAC system; and
a drain of the second current-steering transistor is coupled to a second output of the DAC system.
5. The DAC system of claim 1 , wherein the second current-steering cell of the plurality of current-steering cells comprises:
a third current-steering transistor having a source coupled to the second current source; and
a fourth current-steering transistor having a source coupled to the second current source, wherein a gate of the third current-steering transistor and a gate of the fourth current-steering transistor are coupled to a first output and a second output of a second driver, respectively.
6. The DAC system of claim 5 , wherein the second current-steering cell further comprises:
a fifth current-steering transistor having a source coupled to the second current source; and
a sixth current-steering transistor having a source coupled to the second current source, wherein a gate of the fifth current-steering transistor and a gate of the sixth current-steering transistor are coupled to the first output and the second output of the second driver, respectively.
7. The DAC system of claim 5 , wherein:
the first current-steering cell is configured to process a first bit of a digital input code of the DAC system; and
the second current-steering cell is configured to process a second bit of a digital input code of the DAC system, the first bit having a lower significance than the second bit.
8. The DAC system of claim 5 , wherein:
a first load impedance for the first driver is configured to match a second load impedance for the second driver;
the first load impedance is associated with the first current-steering cell; and
the second load impedance is associated with the second current-steering cell.
9. The DAC system of claim 1 , wherein drains of the first current-steering transistor and the second current-steering transistor are coupled to a resistor-ladder circuit.
10. The DAC system of claim 1 , wherein the first current-steering transistor, the second current-steering transistor, the first transistor, and the second transistor comprise p-channel metal-oxide-semiconductor (PMOS) transistors.
11. A method for digital-to-analog conversion, comprising:
receiving, at a first driver of a digital-to-analog converter (DAC), a first digital input via an input path of the DAC;
generating an analog output signal based on the first digital input by controlling, via the first driver, a first current-steering transistor and a second current-steering transistor of a first current-steering cell of a plurality of current-steering cells based on the first digital input, the first current-steering cell having a first current source coupled to the first current-steering transistor and the second current-steering transistor, wherein the first current-steering cell further comprises:
a first transistor having a source coupled to a current source path, a drain coupled to a reference potential node, and a gate coupled to the first driver; and
a second transistor having a source coupled to the current source path, a drain coupled to the reference potential node, and a gate coupled to the first driver
receiving, via a third transistor of the current source path, a first current at a source of the third transistor, a drain of the third transistor being coupled to the sources of the first transistor and the second transistor; and
providing a second current via a second current source, wherein the first current comprises a first portion of the second current, a second portion of the second current being provided to a second current-steering cell of the plurality of current-steering cells.
12. The method of claim 11 , wherein the first current-steering cell further comprises a fourth transistor coupled between the first current source and a current-steering node, the current-steering node being coupled to sources of the first current-steering transistor and the second current-steering transistor.
13. The method of claim 12 , wherein a gate of the fourth transistor is coupled to a gate of the third transistor.
14. The method of claim 11 , further comprising:
providing, via the first current-steering transistor, a first output current to a first output of the DAC, a drain of the first current-steering transistor being coupled to the first output of the DAC; and
providing, via the second current-steering transistor, a second output current to a second output of the DAC, a drain of the second current-steering transistor being coupled to the second output of the DAC.
15. The method of claim 11 , further comprising:
receiving, at a second driver of the DAC, a second digital input via the input path of the DAC; and
generating the analog output signal based on the second digital input by controlling, via the second driver, a third current-steering transistor and a fourth current-steering transistor of a second current-steering cell of the plurality of current-steering cells based on the second digital input, the second current-steering cell having a second current source coupled to the third current-steering transistor and the fourth current-steering transistor.
16. The method of claim 15 , wherein the second current-steering cell comprises:
a fifth current-steering transistor having a source coupled to the second current source; and
a sixth current-steering transistor having a source coupled to the second current source, wherein a gate of the fifth current-steering transistor and a gate of the sixth current-steering transistor are coupled to a first output and a second output of the second driver, respectively.
17. The method of claim 15 , wherein the first digital input has a lower significance than the second digital input.
18. The method of claim 15 , wherein:
a first load impedance for the first driver is configured to match a second load impedance for the second driver;
the first load impedance is associated with the first current-steering cell; and
the second load impedance is associated with the second current-steering cell.
19. The method of claim 11 , wherein drains of the first current-steering transistor and the second current-steering transistor are coupled to a resistor-ladder circuit.
20. The method of claim 11 , wherein the first current-steering transistor, the second current-steering transistor, the first transistor, and the second transistor comprise p-channel metal-oxide-semiconductor (PMOS) transistors.