Microelectronic assemblies
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
1. A microelectronic assembly, comprising:
a multi-layer structure including multiple layers of dielectric material, wherein the multi-layer structure includes one or more conductive pathways through the dielectric material;
a first die, wherein the first die is conductively coupled to the multi-layer structure;
a second die;
wherein:
the first die is at least partially between the second die and the multi-layer structure,
the first die is bonded to the second die by die-to-die interconnects having a pitch between 7 microns and 100 microns, and
the microelectronic assembly includes interconnects between the second die and the multi-layer structure, wherein the interconnects do not extend through the first die; and
a single mold material over the first die and the second die, the single mold material in contact with a sidewall of the first die, the single mold material having an uppermost surface above an uppermost surface of the second die, and the single mold material on and in contact with the uppermost surface of the second die.
2. The microelectronic assembly of claim 1 , wherein the multi-layer structure includes one or more redistribution layers.
3. The microelectronic assembly of claim 1 , wherein a footprint of the first die is contained within a footprint of the second die.
4. The microelectronic assembly of claim 1 , wherein the first die includes through-substrate vias (TSVs) through a semiconductor substrate of the first die.
5. The microelectronic assembly of claim 1 , wherein the first die is conductively coupled to the multi-layer structure by solder.
6. The microelectronic assembly of claim 1 , wherein the single mold material is between a portion of the second die and the multi-layer structure.
7. The microelectronic assembly of claim 6 , wherein the interconnects extend through the single mold material.
8. The microelectronic assembly of claim 1 , wherein a line from the second die to the multi-layer structure, perpendicular to a plane of a layer of dielectric material of the multi-layer structure, passes through the first die.
9. The microelectronic assembly of claim 1 , wherein the first die is bonded to the second die by metal-to-metal interconnects.
10. The microelectronic assembly of claim 1 , wherein one of the first die and the second die includes memory circuitry and another one of the first die and the second die includes processor circuitry.
11. A microelectronic assembly, comprising:
a package substrate;
a first die, wherein the first die is conductively coupled to the package substrate;
a second die;
wherein:
the first die is at least partially between the second die and the package substrate,
the first die is a memory die,
the second die is a processor die,
the first die is bonded to the second die by first interconnects, wherein the first interconnects are die-to-die interconnects, and
the microelectronic assembly includes second interconnects between the second die and the package substrate, wherein the second interconnects do not extend through the first die; and
a single mold material over the first die and the second die, the single mold material in contact with a sidewall of the first die, the single mold material having an uppermost surface above an uppermost surface of the second die, and the single mold material on and in contact with the uppermost surface of the second die.
12. The microelectronic assembly of claim 11 , wherein the package substrate includes one or more redistribution layers.
13. The microelectronic assembly of claim 11 , wherein a footprint of the first die is contained within a footprint of the second die.
14. The microelectronic assembly of claim 11 , wherein the first die includes through-substrate vias (TSVs) through a semiconductor substrate of the first die.
15. The microelectronic assembly of claim 11 , wherein the first die is conductively coupled to the package substrate by solder.
16. The microelectronic assembly of claim 11 , wherein the single mold material is between a portion of the second die and the package substrate, wherein the interconnects extend through the single mold material.
17. The microelectronic assembly of claim 11 , wherein a line from the second die to the package substrate, perpendicular to a plane of a layer of dielectric material of the package substrate, passes through the first die.
18. The microelectronic assembly of claim 11 , wherein the first die is bonded to the second die by metal-to-metal interconnects.
19. A method of manufacturing a microelectronic assembly, the method including:
forming first interconnects between a first die and a second die, wherein the first interconnects are die-to-die interconnects, and wherein the first die has a first surface and an opposing second surface, the first die includes first conductive contacts at its first surface and second conductive contacts at its first surface, the second die has a first surface and an opposing second surface, the second die includes first conductive contacts at its first surface and second conductive contacts at its second surface, and the first interconnects couple the first conductive contacts of the first die with the second conductive contacts of the second die;
after forming the first interconnects, forming second interconnects between the first conductive contacts of the second die and first conductive contacts of a package substrate, and forming third interconnects between the second conductive contacts of the first die and second conductive contacts of the package substrate; and
forming a single mold material over the first die and the second die, the single mold material in contact with a sidewall of the first die, the single mold material having an uppermost surface above an uppermost surface of the second die, and the single mold material on and in contact with the uppermost surface of the second die.
20. The method of claim 19 , further including:
forming an initial package substrate; and
forming a recess in the initial package substrate;
wherein the first conductive contacts of the package substrate are at a bottom of the recess.