Fast settling voltage regulator
The disclosed voltage regulator circuit includes an NMOS as the main power device that is coupled to a regulated voltage output. A sensing circuit senses the regulated voltage output, and a reference voltage circuit supplies a correct bias to the flipped-source follower, which amplifies the sensed voltage output. A voltage inversion circuit such as a current mirror provides an inverting gain stage for the sensed voltage output, for driving the NMOS. Various other methods, systems, and computer-readable media are also disclosed.
1. A voltage regulator circuit comprising:
a negative-channel metal-oxide semiconductor (NMOS) coupled to a regulated voltage output of the voltage regulator circuit;
a sensing circuit for sensing the regulated voltage output;
a reference voltage circuit for supplying a correct bias voltage to the sensing circuit; and
a voltage inversion circuit coupled between the sensing circuit and the NMOS, wherein the voltage inversion circuit lacks a resistor.
2. The voltage regulator circuit of claim 1 , wherein the sensing circuit comprises a flipped-source follower circuit coupled between the voltage inversion circuit and the reference voltage circuit and configured to amplify the sensed regulated voltage output.
3. The voltage regulator circuit of claim 2 , wherein the flipped-source follower circuit comprises a positive-channel metal-oxide semiconductor (PMOS).
4. The voltage regulator circuit of claim 2 , wherein the flipped-source follower circuit is configured to invert the reference voltage supplied by the reference voltage circuit.
5. The voltage regulator circuit of claim 4 , wherein the voltage inversion circuit is configured to invert the inverted reference voltage from the flipped-source follower circuit.
6. The voltage regulator circuit of claim 5 , wherein the regulated voltage output at the NMOS is not coupled to a capacitor.
7. The voltage regulator circuit of claim 1 , wherein the voltage inversion circuit comprises a current mirror providing an inverting gain stage for the sensed regulated voltage output.
8. The voltage regulator circuit of claim 7 , wherein the current mirror corresponds to an NMOS-based current mirror.
9. The voltage regulator circuit of claim 1 , wherein the NMOS is directly coupled to the regulated voltage output.
10. A device comprising:
a negative-channel metal-oxide semiconductor (NMOS) coupled to a regulated voltage output of a voltage regulator circuit;
a flipped-source follower circuit coupled between a reference voltage circuit and the NMOS for sensing the regulated voltage output;
the reference voltage circuit for supplying a correct bias to the flipped-source follower circuit; and
a voltage inversion circuit coupled between the flipped-source follower circuit and the NMOS, wherein the voltage inversion circuit lacks a resistor.
11. The device of claim 10 , wherein the flipped-source follower circuit comprises a positive-channel metal-oxide semiconductor (PMOS).
12. The device of claim 10 , wherein the flipped-source follower circuit is configured to invert the reference voltage supplied by the reference voltage circuit.
13. The device of claim 12 , wherein the voltage inversion circuit is configured to invert the inverted reference voltage from the flipped-source follower circuit.
14. The device of claim 10 , wherein the voltage inversion circuit comprises a current mirror providing an inverting gain stage of the sensed regulated voltage output.
15. The device of claim 14 , wherein the current mirror corresponds to an NMOS-based current mirror.
16. The device of claim 10 , wherein the NMOS is directly coupled to the regulated voltage output.
17. The device of claim 16 , wherein the regulated voltage output at the NMOS is not coupled to a capacitor.
18. A method comprising:
sensing, by a sensing circuit coupled between a reference voltage circuit for supplying a reference voltage and a voltage regulator circuit comprising a negative-channel metal-oxide semiconductor (NMOS) directly coupled to a voltage output of the voltage regulator circuit, the voltage output;
providing an inverted signal by inverting and amplifying, via a voltage inversion circuit coupled between the sensing circuit and the NMOS, the sensed voltage output from the sensing circuit, wherein the voltage inversion circuit lacks a resistor; and
outputting, via the NMOS, a regulated voltage output based on the inverted signal.
19. The method of claim 18 , further comprising supplying, by the reference voltage circuit, a correct bias to the sensing circuit.
20. The method of claim 18 , further comprising amplifying without inverting, by the sensing circuit, the sensed voltage output.