Systems and methods for assembling processor systems
This disclosure generally relates to processor systems comprising printed circuit boards, I/O chips and processor chips with mated contacts. Contacts are formed on an upper surface of a printed circuit board having a through-hole and on a processor chip inside the through-hole. The processor chip may be a superconducting quantum processor chip comprising qubits, couplers, Digital to Analog converters, QFP shift registers and analog lines. Contacts are formed on an upper surface on an I/O chip and mated with the contacts on the printed circuit board and the processor chip. Contacts may be Indium bump bonds or superconducting solder bonds. The processor chip and the I/O chip may include a shield layer, a substrate layer and a thermally conductive layer.
1. A method of fabricating a processor system, the processor system comprising: a processor chip; a printed circuit board, the printed circuit board having a through-hole with a perimeter that has dimensions that are larger than corresponding dimensions of a perimeter of the processor chip; and an input/output (I/O) chip, the I/O chip having a perimeter that has dimensions that are larger than corresponding dimensions of the through-hole of the printed circuit board, the method comprising:
forming a plurality of contacts on, at, or recessed in a first surface of the processor chip that extend along a perimeter of the processor chip;
forming a plurality of contacts distributed on, at, or recessed in a first surface of the printed circuit board that extend along the perimeter of the through-hole;
forming a first plurality of contacts distributed on, at, or recessed in a first surface around a perimeter of the I/O chip, and a second plurality of contacts distributed on, at, or recessed in the first surface along an inside of the perimeter of the I/O chip;
aligning the processor chip at least partially received inside the through-hole of the printed circuit board;
at least partially covering the first surface of the I/O chip with at least a portion of the first surface of the processor chip and with a least a portion of the first surface of the printed circuit board;
mating the first plurality of contacts on the I/O chip with the plurality of contacts on the printed circuit board and the second plurality of contacts on the I/O chip with the plurality of contacts on the processor chip; and
forming an I/O shield layer below the first and the second plurality of contacts on the I/O chip, the I/O shield layer comprising a material with high critical temperature relative to a material comprising the processor chip, the I/O shield layer including a number of superconducting vias that provide a communicative path to the first and the second plurality of contacts.
2. The method of claim 1 wherein forming the plurality of contacts on, at, or recessed in the first surface of the processor chip, forming the plurality of contacts distributed on, at, or recessed in the first surface of the printed circuit board and forming the first plurality and the second plurality of contacts distributed on, at, or recessed in the first surface of the I/O chip includes forming the plurality of contacts on, at, or recessed in the first surface of the processor chip, forming the plurality of contacts distributed on, at, or recessed in the first surface of the printed circuit board and forming the first plurality and the second plurality of contacts distributed on, at, or recessed in the first surface of the I/O chip selected from a group comprising: Indium bump bonds and superconducting solder bonds.
3. The method of claim 1 wherein forming the plurality of contacts on, at, or recessed in the first surface of the processor chip includes forming the plurality of contacts on, at, or recessed in the first surface of a processor chip comprising a plurality of qubits, couplers, Digital to Analog Converters, QFP shift registers and analog lines; and forming the first plurality and the second plurality of contacts distributed on, at, or recessed in the first surface of the I/O chip includes forming the first plurality and the second plurality of contacts distributed on, at, or recessed in the first surface of a I/O chip comprising Digital to Analog Converters, frequency-multiplexed resonant (FMR) read-in, frequency-multiplexed resonant (FMR) readout, microwave and analog lines.
4. The method of claim 1 further comprising:
forming an I/O substrate layer having a first surface covering a second surface of the I/O chip, the second surface of the I/O chip opposed to the first surface of the I/O chip across a thickness of the I/O chip.
5. The method of claim 4 further comprising:
forming an I/O thermally conductive layer covering a second surface of the I/O substrate layer, the second surface of the I/O substrate layer opposed to the first surface of the I/O substrate layer across a thickness of the I/O substrate layer.
6. The method of claim 5 wherein forming the I/O thermally conductive layer includes forming a thermally conductive layer comprising a material selected from a group consisting of: copper and gold.
7. The method of claim 4 wherein forming the first and the second plurality of contacts distributed on, at, or recessed in the first surface of the I/O chip includes forming the first, and the second plurality of contacts distributed on, at, or recessed in the I/O shield layer.
8. The method of claim 1 wherein forming the I/O shield layer comprising a material with high critical temperature includes forming the I/O shield layer comprising type-II superconductor with a high critical temperature relative to a material comprising the processor chip.
9. The method of claim 1 further comprising forming at least one of: holes and slots, that extend therethrough the I/O shield layer.
10. The method of claim 1 further comprising:
forming a processor shield layer below the plurality of contacts on the processor chip, the processor shield layer comprising a first material with relatively high critical temperature relative to a material comprising the processor chip, the processor shield layer pierced by superconducting vias leading to the contacts.
11. The method of claim 10 wherein forming the processor shield layer, the processor shield layer comprising a first material with relatively high critical temperature relative to a material comprising the processor chip, includes forming the processor shield layer, the processor shield layer comprising a type-II superconductor.
12. The method of claim 10 , further comprising: forming at least one of: holes and slots that extend through the processor shield layer.
13. The method of claim 1 further comprising forming a processor substrate layer having a first surface covering a second surface of the processor chip, the second surface opposed to the first surface of the processor chip across a thickness of the processor chip.
14. The method of claim 13 further comprising forming a processor chip thermally conductive layer covering a second surface of the substrate layer, the second surface of the substrate layer opposed to the first surface of the substrate layer across a thickness of the substrate layer.
15. The method of claim 14 wherein forming the processor chip thermally conductive layer includes forming the processor chip thermally conductive layer a material selected from a group consisting of: copper and gold.
16. The method of claim 1 wherein forming the plurality of contacts distributed on, at, or recessed in the first surface of the printed circuit board includes forming the plurality of contacts distributed on, at, or recessed in a first surface of an assembly of a plurality of printed circuit boards, the printed circuit boards in the plurality of printed circuit boards selected from a group consisting of: a plurality of printed circuit boards, each having a respective through-hole with dimensions larger than corresponding dimensions of the processor chip, the through-holes each approximately centrally located in the printed circuit boards and a plurality of printed circuit boards which collectively define a through-hole, the through-hole having dimensions larger than corresponding dimensions of the processor chip.
17. The method of claim 1 wherein forming the plurality of contacts on, at, or recessed in the first surface of the processor chip includes forming a plurality of bumps on the first surface of the processor chip; forming the plurality of contacts distributed on, at, or recessed in the first surface of the printed circuit board includes forming a plurality of bumps distributed on the first surface of the printed circuit board; and forming the first plurality and the second plurality of contacts distributed on, at, or recessed in the first surface of the I/O chip includes forming a first plurality and a second plurality of pads distributed on, at, or recessed in the first surface of the I/O chip, the plurality of bumps on the printed circuit board able to mate with the first plurality of pads on, at, or recessed in the I/O chip and the plurality of bumps on the processor chip able to mate with the second plurality of pads on, at, or recessed in the I/O chip.
18. The method of claim 1 further comprising: forming a plurality of tiles on the I/O chip, at least one of the tiles in the plurality of tiles comprising a frequency-multiplexed resonant (FMR) readout, at least one of the tiles in the plurality of tiles comprising a FMR read-in; communicatively coupling at least one readout-enabled microwave line to the at least one tile comprising a FMR readout; and communicatively coupling at least one read-in-enabled microwave line to the at least one tile comprising a FMR read-in.
19. The method of claim 18 further comprising: communicatively coupling the FMR readout to at least one other element on the processor chip by at least one of a bump bond and a solder bond and communicatively coupling the FMR read-in to at least one other element on the processor chip by at least one of a bump bond and a solder bond.