Memory program-verify with adaptive sense time based on row location
Technology is disclosed herein for a memory system that includes control circuits that are configured to connect to a three-dimensional memory structure. The memory structure includes NAND strings arranged in a plurality of rows, a plurality of bit lines connected to the NAND strings and a plurality of word lines, each word line coupled to the plurality of rows of NAND strings. The control circuits are configured to, in a program-verify operation, sense memory cells of a first row of NAND strings coupled to the selected word line for a first sense time and sense memory cells of a second row of NAND strings coupled to the selected word line for a second sense time while applying a program-verify voltage to the selected word line.
1. An apparatus comprising:
one or more control circuits configured to connect to a three-dimensional memory structure that includes NAND strings arranged in a plurality of rows, a plurality of bit lines connected to the NAND strings and a plurality of word lines, each word line coupled to the plurality of rows of NAND strings, wherein the one or more control circuits are configured to:
in a program-verify operation, sense memory cells of a first row of NAND strings coupled to a selected word line for a first sense time while applying a program-verify voltage to the selected word line and sense memory cells of a second row of NAND strings coupled to the selected word line for a second sense time while applying the program-verify voltage to the selected word line.
2. The apparatus of claim 1 , wherein the first and second sense times are Verify Low (VL) sense times of a VL verification used to identify memory cells that are close to their target threshold voltage.
3. The apparatus of claim 2 , wherein the one or more control circuits are further configured to perform a Verify High (VH) verification to identify memory cells that have reached their target threshold voltage.
4. The apparatus of claim 3 , wherein the one or more control circuits are configured to sense the memory cells of the first and second rows of NAND strings for a uniform VH sense time.
5. The apparatus of claim 1 , wherein the first row of NAND strings is an edge row of a block and the second row of NAND strings is an interior row of the block.
6. The apparatus of claim 5 , wherein the first sense time is greater than the second sense time.
7. The apparatus of claim 1 , wherein the one or more control circuits are further configured to sense memory cells of a third row of NAND strings coupled to the selected word line for a third sense time while applying the verify voltage to the selected word line.
8. The apparatus of claim 7 , wherein the third row of NAND strings is located between the first and second rows of NAND strings and the third sense time is between the first and second sense times.
9. The apparatus of claim 1 , wherein the one or more control circuits are further configured to slow programming of memory cells of the first row of NAND strings that pass verify using the first sense time and to slow programming of memory cells of the second row of NAND strings that pass verify using the second sense time.
10. The apparatus of claim 9 , wherein the one or more control circuits are further configured to sense the memory cells of the first and second rows of NAND strings for a third sense time and to inhibit further programming of memory cells of the first and second rows of NAND strings that pass verify using the third sense time.
11. A method comprising:
selecting a word line that is coupled to a plurality of rows of NAND strings;
sensing memory cells of a first row of NAND strings coupled to a selected word line for a first sense time while applying a verify voltage to the selected word line; and
sensing memory cells of a second row of NAND strings coupled to the selected word line for a second sense time while applying the verify voltage to the selected word line.
12. The method of claim 11 , wherein the first and second sense times are Verify Low (VL) sense times of a VL verification used to identify memory cells that are close to their target threshold voltage.
13. The method of claim 12 , further comprising:
performing a Verify High (VH) verification using a third sense time to identify memory cells that have reached their target threshold voltage.
14. The method of claim 13 , further comprising:
slowing programming of memory cells of the first and second rows of NAND strings that pass the VL verification; and
inhibiting programming of memory cells of the first and second rows of NAND strings that pass the VH verification.
15. The method of claim 11 , wherein the first row of NAND strings is an edge row of a block and the second row of NAND strings is an interior row of the block.
16. The method of claim 15 , wherein the first sense time is greater than the second sense time.
17. The method of claim 15 , further comprising:
prior to sensing memory cells of the first and second rows of NAND strings, applying one or more program pulses to program the memory cells of the first row at a first programming speed and to program memory cells of the second row at a second programming speed that is greater than the first programming speed.
18. A storage system comprising:
a three-dimensional memory structure that includes NAND strings arranged in a plurality of rows and a plurality of word lines, each word line coupled to the plurality of rows of NAND strings; and
means for sensing first memory cells of a first row of a selected word line for a first Verify Low (VL) sense time and sensing second memory cells of a second row of the selected word line for a second VL sense time in a VL step to identify memory cells approaching their target threshold voltage.
19. The storage system of claim 18 , wherein the first row is an edge row that is adjacent to an isolation region between blocks, the second row is a non-edge row that is not adjacent to an isolation region between blocks and the first VL sense time is longer than the second VL sense time.
20. The storage system of claim 19 , wherein the first memory cells have a first programming speed, the second memory cells have a second programming speed, and the second programming speed is greater than the first programming speed.