A cross-point memory includes a plurality of memory devices, with each device comprising a memory layer between first and second address lines. In one preferred embodiment, the memory layer comprises an OTS (Ovonic Threshold Switch) film and an antifuse film. In another preferred embodiment, the memory layer comprises an OTS film having a first switch voltage (i.e. forming voltage V form ) greater than all subsequent switch voltages (i.e. threshold voltage V th ). The cross-point memory is preferably a three-dimensional one-time-programmable memory (3D-OTP), including horizontal 3D-OTP and vertical 3D-OTP.
1. A three-dimensional memory, comprising:
a semiconductor substrate;
a plurality of first and second address lines above said semiconductor substrate, wherein said first and second address lines intersect each other; and,
a plurality of one-time-programmable memory (OTP) devices disposed at the intersections between said first and second address lines;
each of said devices comprising a memory layer between said first and second address lines, wherein said memory layer comprises at least an OTS film, and the total thickness of said memory layer is smaller than or equal to 60 nm.
2. The memory according to claim 1 , wherein said memory layer further comprises an antifuse film.
3. The memory according to claim 1 , wherein said OTS film has a first switch voltage (forming voltage V form ) greater than all subsequent switch voltages (threshold voltage V th ).
4. The memory according to claim 1 , wherein said OTS film comprises at least a chalcogenide material.
5. The memory according to claim 1 , wherein said first and second address lines are both horizontal address lines, with width smaller than or equal to 60 nm.
6. The memory according to claim 1 , further comprising memory holes penetrating said first address lines, wherein:
said memory layer is formed on the side wall of said memory holes; and,
said second address lines are disposed in said memory holes and surrounded by said memory layer.
7. The memory according to claim 1 , wherein said OTS film is the only active film in said memory layer.
8. The memory according to claim 1 , wherein said memory layer does not comprises any active film other than said OTS film.
9. The memory according to claim 2 , wherein said memory layer further comprises an intermediate-barrier film between said OTS film and said antifuse film.
10. The memory according to claim 1 , wherein said memory layer further comprises a first interface-barrier film between said OTS film and said first/second address lines.
11. The memory according to claim 2 , wherein said memory layer further comprises a second interface-barrier film between said antifuse film and said first/second address lines.