Wafer-on-wafer cascode HEMT device
A semiconductor device includes a first semiconductor structure including a first high electron mobility transistor (HEMT) device, wherein the first HEMT device includes a first gate, a first source, and a first drain; and a second semiconductor structure stacked above and bonded to the first semiconductor structure, wherein the second semiconductor structure includes a second HEMT device and a third HEMT device, wherein the second HEMT device includes a second gate, a second source, and a second drain that is electrically connected to the first source, wherein the third HEMT device includes a third gate, a third source, and a third drain that is electrically connected to the first gate.
1. A semiconductor device comprising:
a first semiconductor structure comprising a first high electron mobility transistor (HEMT) device on a first side of a first substrate, wherein the first HEMT device comprises a first gate, a first source, and a first drain;
a second semiconductor structure stacked above and bonded to the first semiconductor structure, wherein the second semiconductor structure comprises a second HEMT device and a third HEMT device on a first side of a second substrate, wherein the second HEMT device comprises a second gate, a second source, and a second drain that is electrically connected to the first source, wherein the third HEMT device comprises a third gate, a third source, and a third drain that is electrically connected to the first gate, wherein the first side of the first substrate faces the first side of the second substrate; and
an underfill sandwiched between the first semiconductor structure and the second semiconductor structure.
2. The semiconductor device of claim 1 , wherein the second semiconductor structure is bonded to the first semiconductor structure by a plurality of solder bumps.
3. The semiconductor device of claim 1 , wherein the first HEMT device is a depletion mode transistor, the second HEMT device is an enhancement mode transistor, and the third HEMT device is an enhancement mode transistor.
4. The semiconductor device of claim 1 further comprising a first contact structure electrically connected to the first source, a second contact structure electrically connected to the second gate, and a third contact structure electrically connected to the second source, wherein the first contact structure is between the first source and the first gate, the second contact structure is between the second drain and the second gate, and the third contact structure is between the second source and the second gate.
5. The semiconductor device of claim 1 , wherein the second source, the third source, and the third gate are electrically interconnected within the second semiconductor structure.
6. The semiconductor device of claim 1 , wherein the second gate, the third source, and the third gate are electrically interconnected within the second semiconductor structure.
7. The semiconductor device of claim 1 , wherein the first gate comprises a gate electrode over a layer of p-doped gallium nitride.
8. The semiconductor device of claim 1 , wherein the first semiconductor structure comprises a silicon substrate, a channel layer over the silicon substrate comprising gallium nitride, and an active layer over the channel layer comprising aluminum gallium nitride.
9. The semiconductor device of claim 8 , wherein the channel layer has a thickness that is less than 5 μm.
10. A package comprising:
a first semiconductor structure comprising a first high electron mobility transistor (HEMT) device formed on a first side of a first substrate;
a second semiconductor structure comprising a second HEMT device and a third HEMT device formed on a first side of a second substrate, wherein the second semiconductor structure is attached to the first semiconductor structure, wherein the first HEMT device, the second HEMT device, and the third HEMT device are connected in a cascode configuration;
a first conductive feature extending over a second side of the first substrate, wherein the first conductive feature penetrates the first substrate to electrically connect to the first HEMT device;
a second conductive feature extending over a second side of the second substrate, wherein the second conductive feature penetrates the second substrate to electrically connect to the second HEMT device; and
a third conductive feature extending over the second side of the second substrate, wherein the third conductive feature penetrates the second substrate to electrically connect to the second HEMT device.
11. The package of claim 10 further comprising a leadframe, wherein the leadframe comprises a conductive die pad and a plurality of conductive leads, wherein the first conductive feature is attached to the conductive die pad.
12. The package of claim 11 , wherein a first conductive lead is electrically connected to the first conductive feature by the conductive die pad, wherein a second conductive lead is electrically connected to the second conductive feature by a first metal plate, wherein a third conductive lead is electrically connected to the third conductive feature by a second metal plate.
13. The package of claim 12 , wherein a fourth conductive lead is electrically connected to the third conductive feature by the second metal plate.
14. The package of claim 10 further comprising a first heatsink over the first substrate and a second heatsink over the second substrate opposite the first substrate.
15. The package of claim 10 , wherein the second conductive feature is electrically connected to a gate contact of the second HEMT device, wherein the third conductive feature is electrically connected to a source contact of the second HEMT device.
16. A method comprising:
forming a first high electron mobility transistor (HEMT) device on a first semiconductor substrate;
forming a first interconnect structure over the first semiconductor substrate, wherein the first interconnect structure is electrically connected to the first HEMT device;
forming a second HEMT device and a third HEMT device on a second semiconductor substrate;
forming a second interconnect structure over the second semiconductor substrate, wherein the second interconnect structure electrically connects the second HEMT device to the third HEMT device; and
bonding the first interconnect structure to the second interconnect structure using solder bumps, wherein a first solder bump electrically connects the first HEMT device to the second HEMT device and a second solder bump electrically connects the first HEMT device to the third HEMT device.
17. The method of claim 16 , wherein the bonding electrically connects a source of the first HEMT device to a drain of the second HEMT device and electrically connects a gate of the first HEMT device to a drain of the third HEMT device.
18. The method of claim 16 further comprising forming seal ring structures in the first interconnect structure.
19. The package of claim 10 , wherein the first side of the first substrate is closer to the first side of the second substrate than to the second side of the second substrate.