Memory devices having vertical transistors and methods for forming the same
In certain aspects, a memory device includes a vertical transistor, a storage unit, and a bit line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and in contact with a second terminal. The second terminal is another one of the source and the drain that is formed on one or some sides, but not all sides, of a protrusion of the semiconductor body. The bit line is separated from the channel portion of the semiconductor body by the second terminal.
1 . A memory device, comprising:
a vertical transistor comprising a semiconductor body extending in a first direction, the semiconductor body comprising a doped source, a doped drain, and a channel portion;
a storage unit coupled to a first terminal, the first terminal being one of the source and the drain; and
a bit line extending in a second direction perpendicular to the first direction and in contact with a second terminal, the second terminal being another one of the source and the drain that is formed on one or some sides, but not all sides, of a protrusion of the semiconductor body,
wherein:
the protrusion of the semiconductor body is connected with a body line that continuously extends in a third direction perpendicular to the first and second directions;
the second terminal comprises a first portion that directly contacts a sidewall of the bit line, and a second portion that directly contacts a bottom surface of the bit line;
a gate dielectric in a gate structure of the vertical transistor covers a sidewall of a base of the semiconductor body connected with the protrusion, and a dielectric layer is arranged on the bit line at a side opposite to the second portion of the second terminal, and in the third direction, a width of the dielectric layer is approximately equal to a width of the bit line, and a width of the first terminal and a thickness of the gate dielectric are approximately equal to widths of the bit line, the first portion of the second terminal, and the protrusion;
a projection of the bit line and a projection of the second terminal overlap on a plane perpendicular to the first direction, and the projection of the bit line and a projection of the first terminal overlap on the plane; and
the bit line is separated from the channel portion of the semiconductor body by the second terminal.
2 . The memory device of claim 1 , wherein the bit line partially circumscribes the protrusion of the semiconductor body in a plan view.
3 . The memory device of claim 1 , wherein
the first terminal is formed on one end of the base of the semiconductor body; and
the channel portion is formed in the base and the protrusion of the semiconductor body.
4 . The memory device of claim 1 , wherein the body line is coupled to the channel portion of the semiconductor body.
5 . The memory device of claim 4 , wherein the body line and the storage unit are coupled to opposite ends of the vertical transistor in the first direction.
6 . The memory device of claim 4 , wherein the bit line is between the storage unit and the body line in the first direction.
7 . The memory device of claim 4 , wherein the body line comprises a polysilicon layer in contact with the channel portion of the semiconductor body, and a metal layer in contact with the polysilicon layer.
8 . The memory device of claim 1 , wherein the semiconductor body comprises single crystalline silicon, and the channel portion comprises undoped single crystalline silicon or doped single crystalline silicon having a different type of dopant from the source and the drain.
9 . The memory device of claim 1 , further comprising:
a word line extending in the third direction perpendicular to the first direction and the second direction, wherein the vertical transistor further comprises the gate structure in contact with one or more sides of the semiconductor body in the third direction.
10 . The memory device of claim 9 , wherein the gate structure comprises the gate dielectric in contact with the protrusion of the semiconductor body.
11 . The memory device of claim 1 , wherein:
the first portion extends in the first direction and the second portion extends in the third direction, a projection of the second portion overlapping with the projection of the bit line.
12 . The memory device of claim 1 , wherein:
the second terminal is in direct contact with the protrusion and the base of the semiconductor body, the base having a lateral dimension larger than the protrusion.
13 . The memory device of claim 1 , wherein:
in a plan view, the bit line is arranged at a single side of the channel portion, a bottom of the second terminal being lower than a bottom of the bit line.
14 . The memory device of claim 1 , wherein:
the vertical transistor further comprises the gate structure; and
in a cross-section along a word line, the gate dielectric of the gate structure covers one side of the protrusion and extends, in the first direction, to cover the sidewall of the base of the semiconductor body that has a lateral dimension larger than the protrusion.
15 . The memory device of claim 14 , wherein:
another side of the protrusion is in direct contact with the second terminal.
16 . A memory system, comprising:
a memory device configured to store data, and comprising:
a vertical transistor comprising a semiconductor body extending in a first direction, the semiconductor body comprising a doped source, a doped drain, and a channel portion;
a storage unit coupled to a first terminal, the first terminal being one of the source and the drain; and
a bit line extending in a second direction perpendicular to the first direction and in contact with a second terminal, the second terminal being another one of the source and the drain that is formed on one or some sides, but not all sides, of a protrusion of the semiconductor body,
wherein:
a projection of the bit line and a projection of the second terminal overlap on a plane perpendicular to the first direction, and the projection of the bit line and a projection of the first terminal overlap on the plane;
the bit line is separated from the channel portion of the semiconductor body by the second terminal;
the second terminal comprises a first portion that directly contacts a sidewall of the bit line, and a second portion that directly contacts a bottom surface of the bit line; and
a gate dielectric in a gate structure of the vertical transistor covers a sidewall of a base of the semiconductor body connected with the protrusion, and a dielectric layer is arranged on the bit line at a side opposite to the second portion of the second terminal, and in a third direction perpendicular to the first and second directions, a width of the dielectric layer is approximately equal to a width of the bit line, and a width of the first terminal and a thickness of the gate dielectric are approximately equal to widths of the bit line, the first portion of the second terminal, and the protrusion; and
a memory controller coupled to the memory device and configured to control the vertical transistor and the storage unit through the bit line.
17 . A memory device, comprising:
a vertical transistor comprising a semiconductor body extending in a first direction, the semiconductor body comprising a doped source, a doped drain, and a channel portion;
a storage unit coupled to a first terminal, the first terminal being one of the source and the drain; and
a bit line extending in a second direction perpendicular to the first direction and in contact with a second terminal, the second terminal being another one of the source and the drain that is formed on one or some sides, but not all sides, of a protrusion of the semiconductor body,
wherein:
the second terminal comprises a first portion that directly contacts a sidewall of the bit line and a second portion extending laterally to partially cover a bottom surface of the bit line;
a gate dielectric in a gate structure of the vertical transistor covers a sidewall of a base of the semiconductor body connected with the protrusion, and a dielectric layer is arranged on the bit line at a side opposite to the second portion of the second terminal, and in a third direction perpendicular to the first and second directions, a width of the dielectric layer is approximately equal to a width of the bit line, and a width of the first terminal and a thickness of the gate dielectric are approximately equal to widths of the bit line, the first portion of the second terminal, and the protrusion;
a projection of the bit line and a projection of the second terminal overlap on a plane perpendicular to the first direction, and the projection of the bit line and a projection of the first terminal overlap on the plane; and
the bit line is separated from the channel portion of the semiconductor body by the second terminal.
18 . The memory device of claim 17 , wherein:
the projection of the bit line and a projection of the semiconductor body overlap on the plane.
19 . The memory device of claim 17 , wherein:
the semiconductor body comprises the base that has a dimension larger than the protrusion, and the protrusion protruding, in the first direction, from the base; and
the vertical transistor further comprises the gate structure, the gate dielectric of the gate structure extending continuously in the first direction to cover a sidewall of the protrusion, a sidewall of the first terminal, and the sidewall of the base.
20 . The memory device of claim 17 , wherein:
the semiconductor body comprises the base that has a dimension larger than the protrusion, and the protrusion protruding, in the first direction, from the base; and
in the first direction, the second terminal is sandwiched between the bit line and the base.