Bipolar junction transistor arrays
Structures that include bipolar junction transistors and methods of forming such structures. The structure comprises a semiconductor layer, a substrate, and a dielectric layer disposed between the semiconductor layer and the substrate. The structure further comprises a first bipolar junction transistor including a first collector in the substrate, a first emitter, and a first base layer. The first base layer extends through the dielectric layer from the first emitter to the first collector. The structure further comprises a second bipolar junction transistor including a second collector in the substrate, a second emitter, and a second base layer. The second base layer extends through the dielectric layer from the second emitter to the second collector. The second base layer is connected to the first base layer by a section of the semiconductor layer to define a base line.
1 . A structure comprising:
a semiconductor layer including a first section;
a substrate;
a dielectric layer disposed between the semiconductor layer and the substrate;
a first bipolar junction transistor including a first collector in the substrate, a first emitter, and a first base layer positioned between the first collector and the first emitter, the first base layer extending through the dielectric layer from the first emitter to the first collector;
a second bipolar junction transistor including a second collector in the substrate, a second emitter, and a second base layer positioned between the second collector and the second emitter, the second base layer extending through the dielectric layer from the second emitter to the second collector, and the second base layer connected to the first base layer by the first section of the semiconductor layer to define a first base line; and
a dummy gate structure positioned between the first emitter and the second emitter.
2 . The structure of claim 1 further comprising:
a first well in the substrate; and
a second well in the substrate,
wherein the first collector is a portion of the first well, and the second collector is a portion of the second well.
3 . The structure of claim 2 wherein the first well is separated from the second well by a portion of the substrate.
4 . The structure of claim 3 wherein the first well and the second well have n-type conductivity, and the portion of the substrate has p-type conductivity.
5 . The structure of claim 2 further comprising:
a trench isolation region extending through the semiconductor layer and the dielectric layer into the substrate, the trench isolation region positioned between the first well and the second well.
6 . The structure of claim 2 further comprising:
a third bipolar junction transistor including a third collector in the substrate, a third emitter, and a third base layer, the third base layer extending through the dielectric layer from the third emitter to the third collector; and
a trench isolation region positioned between the first base layer and the third base layer.
7 . The structure of claim 6 wherein the trench isolation region extends into the first well.
8 . The structure of claim 6 wherein the trench isolation region is positioned in a lateral direction between the first emitter and the third emitter.
9 . The structure of claim 2 wherein the first well and the second well are longitudinally aligned orthogonal to the first base line.
10 . The structure of claim 1 wherein the dummy gate structure is positioned on the first section of the semiconductor layer.
11 . The structure of claim 1 further comprising:
a first memory element connected to the first emitter of the first bipolar junction transistor; and
a second memory element connected to the second emitter of the second bipolar junction transistor.
12 . The structure of claim 11 further comprising:
an interconnect structure over the first bipolar junction transistor and the second bipolar junction transistor, the interconnect structure including a plurality of dielectric layers in a layer stack,
wherein the first memory element and the second memory element are positioned in the interconnect structure.
13 . The structure of claim 11 wherein the first memory element and the second memory element each include a first electrode, a second electrode, and a switching layer positioned between the first electrode and the second electrode.
14 . A structure comprising:
a semiconductor layer including a first section and a second section;
a substrate;
a dielectric layer disposed between the semiconductor layer and the substrate;
a first well in the substrate;
a second well in the substrate;
a first bipolar junction transistor including a first collector in the substrate, a first emitter, and a first base layer positioned between the first collector and the first emitter, the first base layer extending through the dielectric layer from the first emitter to the first collector;
a second bipolar junction transistor including a second collector in the substrate, a second emitter, and a second base layer positioned between the second collector and the second emitter, the second base layer extending through the dielectric layer from the second emitter to the second collector, and the second base layer connected to the first base layer by the first section of the semiconductor layer to define a first base line;
a third bipolar junction transistor positioned adjacent to the first bipolar junction transistor, the third bipolar junction transistor including a third collector in the substrate, a third emitter, and a third base layer, and the third base layer extending through the dielectric layer from the third emitter to the third collector; and
a fourth bipolar junction transistor including a fourth collector in the substrate, a fourth emitter, and a fourth base layer positioned between the fourth collector and the fourth emitter, the fourth base layer extending through the dielectric layer from the fourth emitter to the fourth collector, and the fourth base layer connected to the third base layer by the second section of the semiconductor layer to define a second base line,
wherein the first collector and the third collector are portions of the first well, and the second collector and the fourth collector are portions of the second well.
15 . The structure of claim 14 further comprising:
a trench isolation region positioned between the first base line and the second base line.
16 . The structure of claim 1 wherein the first collector, the first emitter, the second collector, and the second emitter have n-type conductivity, and the first base layer and the second base layer have p-type conductivity.
17 . A method comprising:
forming a first bipolar junction transistor including a first collector in a substrate, a first emitter, and a first base layer positioned between the first collector and the first emitter, wherein a dielectric layer is disposed between a semiconductor layer and the substrate, and the first base layer extends through the dielectric layer from the first emitter to the first collector; and
forming a second bipolar junction transistor including a second collector in the substrate, a second emitter, and a second base layer positioned between the second collector and the second emitter, wherein the second base layer extends through the dielectric layer from the second emitter to the second collector, and the second base layer is connected to the first base layer by a section of the semiconductor layer to define a base line,
wherein a dummy gate structure is positioned between the first emitter and the second emitter.
18 . The structure of claim 14 further comprising:
a first memory element connected to the first emitter of the first bipolar junction transistor;
a second memory element connected to the second emitter of the second bipolar junction transistor;
a third memory element connected to the third emitter of the third bipolar junction transistor; and
a fourth memory element connected to the fourth emitter of the fourth bipolar junction transistor.
19 . The structure of claim 14 wherein the first well is separated from the second well by a portion of the substrate.
20 . The structure of claim 14 further comprising:
a trench isolation region extending through the semiconductor layer and the dielectric layer into the substrate, the trench isolation region positioned between the first well and the second well.