Horizontal GAA nano-wire and nano-slab transistors
Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a doped semiconductor material between source regions and drain regions of the device. The method includes doping semiconductor material layers between source regions and drain regions of an electronic device.
1 . A horizontal gate-all-around device comprising a plurality of horizontal doped semiconductor material layers between a source region and a drain region on a substrate, the plurality of horizontal doped semiconductor material layers having a homogeneous concentration of dopant.
2 . The device of claim 1 , wherein the homogeneous concentration of dopant is in a range of from about 10 17o atoms/cm 3 to about 10 21 atoms/cm 3 throughout the thickness of the plurality of horizontal doped semiconductor material layers.
3 . The device of claim 1 , wherein the dopant comprises about 10 19 atoms/cm 3 of boron.
4 . The device of claim 1 , wherein the device has a gate voltage greater than or equal to about 0.400 V.
5 . The device of claim 4 , wherein the gate voltage required to turn on the device is greater than or equal to about 140% of the gate voltage required to turn on a device without the dopant.
6 . The device of claim 4 , wherein the gate voltage required to turn on the device is in the range of 1 to 2 times the gate voltage to turn on a device without the dopant.
7 . The device of claim 1 , further comprising a superlattice structure on a top surface of a substrate.
8 . The device of claim 7 , wherein the source region is adjacent a first end of the superlattice structure and the drain region is adjacent a second opposing end of the superlattice structure.
9 . The device of claim 7 , wherein the superlattice structure comprises the plurality of horizontal doped semiconductor material layers, an oxide layer on the plurality of horizontal doped semiconductor material layers, a high-k dielectric layer on the oxide layer, and conductive layer on the high-k dielectric layer.
10 . The device of claim 9 , wherein the conductive layer comprises one of more of titanium nitride, tungsten, cobalt, and aluminum.
11 . The device of claim 9 , wherein the conductive layer has a uniform thickness around each of the plurality of horizontal doped semiconductor material layers.
12 . The device of claim 7 , further comprising a gate electrode on the substrate and surrounding each of the plurality of horizontal doped semiconductor material layers.
13 . A horizontal gate-all-around device comprising:
a superlattice structure between a source region and a drain region on a substrate, the superlattice structure comprising a plurality of horizontal doped semiconductor material layers, an oxide layer on the plurality of horizontal doped semiconductor material layers, a high-k dielectric layer on the oxide layer, and conductive layer on the high-k dielectric layer, the plurality of horizontal doped semiconductor material layers having a homogeneous concentration of dopant; and
a gate electrode on the substrate and surrounding each of the plurality of horizontal doped semiconductor material layers.
14 . The device of claim 13 , wherein the source region is adjacent a first end of the superlattice structure and the drain region is adjacent a second opposing end of the superlattice structure.
15 . The device of claim 13 , wherein the homogeneous concentration of dopant is in a range of from about 10 17 atoms/cm 3 to about 10 21 atoms/cm 3 throughout the thickness of the plurality of horizontal doped semiconductor material layers.
16 . The device of claim 13 , wherein the dopant comprises about 10 19 atoms/cm 3 of boron.
17 . The device of claim 13 , wherein the device has a gate voltage greater than or equal to about 0.400 V.
18 . The device of claim 17 , wherein the gate voltage required to turn on the device is greater than or equal to about 140% of the gate voltage required to turn on a device without the dopant.
19 . The device of claim 17 , wherein the gate voltage required to turn on the device is in the range of 1 to 2 times the gate voltage to turn on a device without the dopant.
20 . The device of claim 13 , wherein the conductive layer has a uniform thickness around each of the plurality of horizontal doped semiconductor material layers.