Semiconductor devices
A semiconductor device includes a channel on a substrate. The channel includes a 2-dimensional material. A gate insulating layer is on a first portion of the channel. A gate electrode is on a portion of the gate insulating layer. First and second contact patterns are on second portions of the channel, respectively. Each of the first and second contact patterns includes a 2-dimensional material having an intercalation material disposed therein. First and second source/drain electrodes are on the first and second contact patterns, respectively. Each of the first and second source/drain electrodes includes a metal.
1 . A semiconductor device, comprising:
a channel on a substrate, the channel including a 2-dimensional material;
a gate insulating layer on a first portion of the channel;
a gate electrode on a portion of the gate insulating layer;
first and second contact patterns on second portions of the channel, respectively, each of the first and second contact patterns including a 2-dimensional material having an intercalation material disposed therein; and
first and second source/drain electrodes on the first and second contact patterns, respectively, each of the first and second source/drain electrodes including a metal,
wherein the gate insulating layer covers a lower surface and a sidewall of the gate electrode.
2 . The semiconductor device of claim 1 , wherein each of the first and second contact patterns includes a transition metal dichalcogenide (TMD) containing a transition metal and a chalcogen element.
3 . The semiconductor device of claim 2 , wherein the transition metal includes at least one element selected from molybdenum (Mo), tungsten (W), rhenium (Re), niobium (Nb), vanadium (V), tantalum (Ta), titanium (Ti), zirconium (Zr) hafnium (Hf) and technetium (Tc).
4 . The semiconductor device of claim 2 , wherein the chalcogen element includes at least one element selected from sulfur(S), selenium (Se), and tellurium (Te).
5 . The semiconductor device of claim 2 , wherein the transition metal dichalcogenide (TMD) includes molybdenum sulfide (MoS 2 ).
6 . The semiconductor device of claim 1 , wherein each of the first and second contact patterns has a multi-layered structure including a plurality of single layers stacked in a vertical direction substantially perpendicular to an upper surface of the substrate, each of the single layers including a 2-dimensional material and the intercalation material is disposed between the single layers.
7 . The semiconductor device of claim 6 , wherein the intercalation material includes lithium (Li).
8 . The semiconductor device of claim 1 , wherein the channel and the first and second contact patterns include a substantially same 2-dimensional material.
9 . The semiconductor device of claim 1 , further comprising:
a first contact plug on the gate electrode; and
second and third contact plugs on the first and second source/drain electrodes, respectively.
10 . The semiconductor device of claim 1 , wherein the gate insulating layer covers a sidewall of each of the first and second contact patterns, and a sidewall and an upper surface of each of the first and second source/drain electrodes.
11 . The semiconductor device of claim 1 , further comprising an insulating layer positioned between the substrate and the channel.
12 . A semiconductor device, comprising:
a channel on a substrate, the channel including a transition metal dichalcogenide (TMD) containing a transition metal and a chalcogen element;
a gate insulating layer on a first portion of the channel;
a gate electrode on a first portion of the gate insulating layer;
first and second contact patterns on second portions of the channel, respectively; and
first and second source/drain electrodes on the first and second contact patterns, respectively, each of the first and second source/drain electrodes includes a metal,
wherein each of the first and second contact patterns has a multi-layered structure including single layers stacked in a vertical direction substantially perpendicular to an upper surface of the substrate, each of the single layers including a transition metal dichalcogenide (TMD), and an intercalation material disposed between the single layers.
13 . The semiconductor device of claim 12 , wherein the transition metal includes at least one element selected from molybdenum (Mo), tungsten (W), rhenium (Re), niobium (Nb), vanadium (V), tantalum (Ta), titanium (Ti), zirconium (Zr) hafnium (Hf) and technetium (Tc).
14 . The semiconductor device of claim 12 , wherein the chalcogen element includes at least one element selected from sulfur(S), selenium (Se), and tellurium (Te).
15 . The semiconductor device of claim 12 , wherein the transition metal dichalcogenide (TMD) includes molybdenum sulfide (MoS 2 ).
16 . The semiconductor device of claim 12 , wherein the intercalation material includes lithium (Li).
17 . The semiconductor device of claim 15 , wherein the channel and the first and second contact patterns include a substantially same 2-dimensional material.
18 . The semiconductor device of claim 12 , further comprising:
second and third contact plugs contacting upper surfaces of the first and second source/drain electrodes, respectively, and including a metal.
19 . A semiconductor device, comprising:
an insulating layer on a substrate;
a channel on the insulating layer, the channel including a 2-dimensional material;
first and second contact patterns on upper edge surfaces, respectively, of the channel, each of the first and second contact patterns including a 2-dimensional material having an intercalation material disposed therein;
first and second source/drain electrodes on the first and second contact patterns, respectively, each of the first and second source/drain electrodes including a metal;
a gate insulating layer on an upper central surface and sidewalls of the channel, sidewalls of the first and second contact patterns, and sidewalls and upper surfaces of the first and second source/drain electrodes;
a gate electrode on the gate insulating layer on the upper central surface of the channel, wherein a lower surface and a sidewall of the gate electrode are covered by the gate insulating layer;
a first contact plug directly contacting an upper surface of the gate electrode; and
second and third contact plugs extending through the gate insulating layer and directly contacting upper surfaces of the first and second source/drain electrodes, respectively.