IP Library › Granted Patent US 12,490,426
Granted Patent B2
US 12,490,426 · App. 18/184,532 · Granted Dec 2, 2025

Semiconductor memory device and manufacturing method thereof

Inventors: Seung Wook Ryu (Yongin-si, KR); Ki Hong Lee (Suwon-si, KR)
Assignee: SK hynix Inc.
H10B41/27H10B43/27H10B63/34
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,490,426
App. No.
18/184,532
Granted
Dec 2, 2025
Kind
B2
Abstract

A semiconductor memory device includes a first source layer, a second source layer on the first source layer, a stack structure over the second source layer, and a common source line penetrating the stack structure. The second source layer includes a protective layer in contact with the common source line and a conductive layer surrounding the protective layer.

Claims (39)

1 . A method of manufacturing a semiconductor memory device, the method comprising:

forming a source structure including a source sacrificial structure;

forming a stack structure on the source structure;

forming a trench penetrating the stack structure;

forming a first cavity by removing the source sacrificial structure through the trench;

forming a preliminary conductive layer including a first preliminary conductive part in the trench and a second preliminary conductive part in the first cavity;

forming a first protective layer over the first preliminary conductive part and in a second cavity surrounded by the second preliminary conductive part;

removing a portion of the first protective layer in the trench and the second cavity to form a third cavity exposing a sidewall of the first protective layer in the second cavity; and

removing the first preliminary conductive part and a portion of the second preliminary conductive part to expand the third cavity.

2 . The method of claim 1 , wherein forming the first protective layer includes:

forming a first preliminary protective part in the trench; and

forming a second preliminary protective part in the first cavity.

3 . The method of claim 2 , wherein removing the portion of the first protective layer includes removing the first preliminary protective part.

4 . The method of claim 3 , wherein removing the first preliminary protective part includes forming an oxidation part by oxidizing the first preliminary protective part.

5 . The method of claim 4 , wherein removing the first preliminary protective part further includes removing the oxidation part.

6 . The method of claim 3 , wherein removing the first preliminary protective part includes etching the first preliminary protective part.

7 . The method of claim 1 , further comprising forming a channel structure penetrating the stack structure.

8 . The method of claim 7 , wherein the channel structure is formed to include a channel layer in contact with the second preliminary conductive part.

9 . A method of manufacturing a semiconductor memory device, the method comprising:

forming a source sacrificial structure;

alternately stacking insulating layers and gate sacrificial layers over the source sacrificial structure;

forming a trench penetrating the insulating layers and the gate sacrificial layers;

forming a first cavity by removing the source sacrificial structure through the trench;

forming a source layer including a conductive layer in the first cavity and a protective layer in a second cavity of the conductive layer;

forming a third cavity in the first cavity by removing a portion of the protective layer in the second cavity, wherein the third cavity is connected to the trench;

removing the gate sacrificial layers between the insulating layers, wherein the protective layer overlaps each area in which the gate sacrificial layers are removed;

forming gate patterns between the insulating layers; and

forming a common source line in the third cavity and the trench, wherein the common source line is coupled to the source layer.

10 . The method of claim 9 , wherein forming the source layer includes forming a preliminary conductive layer including the second cavity in the first cavity.

11 . The method of claim 10 , wherein forming the source layer further includes forming a preliminary protective layer in the second cavity.

12 . The method of claim 9 , further comprising forming a channel structure penetrating the source sacrificial structure, the insulating layers, and the gate sacrificial layers.

13 . The method of claim 9 , wherein forming the source layer includes:

forming a preliminary conductive layer including a first preliminary conductive part in the first cavity and a second preliminary conductive part in the trench; and

forming a preliminary protective layer in the preliminary conductive layer.

14 . The method of claim 13 , wherein forming the preliminary protective layer includes forming a first preliminary protective part in the first cavity and a second preliminary protective part in the trench.

15 . The method of claim 14 , wherein forming the source layer further includes removing the second preliminary protective part.

16 . The method of claim 15 , wherein removing the second preliminary protective part includes forming an oxidation part by oxidizing the second preliminary protective part.

17 . The method of claim 16 , wherein removing the second preliminary protective part further includes removing the oxidation part.

18 . The method of claim 15 , wherein removing the second preliminary protective part includes etching the second preliminary protective part.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2023
From: RYU, SEUNG WOOK; LEE, KI HONG
To: SK HYNIX INC.
Reel/Frame 062995/0404 →
Priority Claims (1)
KR 10-2019-0161366 · Dec 6, 2019 · national
Continuity (2)
Continuation 16883721 · May 26, 2020
Related Publication 20230217652A1 · Jul 6, 2023
References Cited (32)
US 8877590B1 · Lee · 2014 [cited by applicant]
US 9831266B2 · Kai et al. · 2017 [cited by applicant]
US 10559591B2 · Kanamori et al. · 2020 [cited by applicant]
US 20150155296A1 · Yoon · 2015 [cited by applicant]
US 20150333143A1 · Meldrim et al. · 2015 [cited by applicant]
US 20170162594A1 · Ahn · 2017 [cited by applicant]
US 20170207226A1 · Lee · 2017 [cited by applicant]
US 20180138195A1 · Lee · 2018 [cited by applicant]
US 20180366486A1 · Hada et al. · 2018 [cited by applicant]
US 20180374866A1 · Makala et al. · 2018 [cited by applicant]
US 20190157294A1 · Kanamori et al. · 2019 [cited by applicant]
US 20190172906A1 · Kim et al. · 2019 [cited by applicant]
US 20190288000A1 · Choi · 2019 [cited by applicant]
US 20190319041A1 · Kwak et al. · 2019 [cited by applicant]
US 20190333931A1 · Jung et al. · 2019 [cited by applicant]
US 20200350168A1 · Kim et al. · 2020 [cited by applicant]
US 20200411536A1 · Kim et al. · 2020 [cited by applicant]
US 20210193675A1 · Howder et al. · 2021 [cited by applicant]
CN 102760739A · 2012 [cited by applicant]
CN 104835824A · 2015 [cited by applicant]
CN 105845630A · 2016 [cited by applicant]
CN 106856198A · 2017 [cited by applicant]
CN 107293544A · 2017 [cited by applicant]
CN 107425005A · 2017 [cited by applicant]
CN 108063142A · 2018 [cited by applicant]
CN 109346477A · 2019 [cited by applicant]
CN 109659308A · 2019 [cited by applicant]
JP 2002353344A · 2002 [cited by applicant]
KR 1020180003191A · 2018 [cited by applicant]
KR 1020190041708A · 2019 [cited by applicant]
KR 1020190107975A · 2019 [cited by applicant]
KR 1020190119439A · 2019 [cited by applicant]