IP Library › Granted Patent US 12,500,083
Granted Patent B2
US 12,500,083 · App. 17/771,042 · Granted Dec 16, 2025

Wiring substrate, electronic device, and electronic module

Inventors: Seiichirou Itou (Kyoto, JP); Yuichiro Ishizaki (Kyoto, JP); Haruki Umeki (Kyoto, JP)
Assignee: KYOCERA Corporation
H01L21/02433H01L21/02378H01L21/0262H10D62/405H10D62/8325
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Quick Facts
Patent No.
US 12,500,083
App. No.
17/771,042
Granted
Dec 16, 2025
Kind
B2
Abstract

A wiring substrate includes an insulating substrate including a first surface and a wiring conductor located at the insulating substrate, the insulating substrate containing multiple bulk crystallites of SiC with different polytypes. An electronic device includes the wiring substrate described above and an electronic component mounted on the wiring substrate. An electronic module includes the electronic device described above and a module substrate on which the electronic device is mounted.

Claims (41)

1 . A wiring substrate, comprising:

an insulating substrate including a first surface; and

a wiring conductor located at the insulating substrate,

wherein the insulating substrate contains multiple bulk crystallites of SiC with different polytypes,

wherein the insulating substrate includes a first bulk crystallite and a second bulk crystallite adjacent to each other, and

wherein the first bulk crystallite includes a micropipe including an end portion blocked by the second bulk crystallite.

2 . The wiring substrate according to claim 1 , wherein

the insulating substrate contains at least any of a 4H-type bulk crystallite, a 6H-type bulk crystallite, and a 15R-type bulk crystallite, and

a total volume fraction of the 4H-type bulk crystallite, the 6H-type bulk crystallite, and the 15R-type bulk crystallite is 80% or more.

3 . The wiring substrate according to claim 1 ,

wherein a volume fraction of 3C-type bulk crystallites is 1% or less.

4 . The wiring substrate according to claim 1 ,

wherein the multiple bulk crystallites further include a third bulk crystallite and a fourth bulk crystallite having different plane directions from each other.

5 . The wiring substrate according to claim 1 ,

wherein the insulating substrate further include a fifth bulk crystallite including a micropipe extending in a first direction and a sixth bulk crystallite including a micropipe extending in a second direction different from the first direction.

6 . The wiring substrate according to claim 1 , wherein

the insulating substrate includes a second surface opposite to the first surface, and

the insulating substrate includes a grain boundary-free portion extending from the first surface to the second surface.

7 . The wiring substrate according to claim 1 ,

wherein the insulating substrate has a resistivity of 1×10 3 Ω·cm or more.

8 . The wiring substrate according to claim 1 , wherein

the multiple bulk crystallites further include a seventh bulk crystallite and an eighth bulk crystallite adjacent to each other, and

no grain boundary phase is present between the seventh bulk crystallite and the eighth bulk crystallite.

9 . The wiring substrate according to claim 1 , wherein

the wiring substrate is a submount including the wiring conductor located at the insulating substrate,

the first surface includes a mounting portion on which an electronic component serving as a light-emitting element is mounted, and

the insulating substrate has a smaller average thickness in a thickness direction than a maximum width in a planar direction along the first surface.

10 . An electronic device, comprising:

the wiring substrate according to claim 1 ; and

an electronic component mounted on the wiring substrate.

11 . A wiring substrate comprising:

an insulating substrate including a first surface; and

a wiring conductor located at the insulating substrate,

wherein the insulating substrate contains multiple bulk crystallites of SiC with different polytypes, and

wherein a number of the multiple bulk crystallites on the first surface is 2 pieces/cm 2 or more and 100 pieces/cm 2 or less.

12 . A wiring substrate comprising:

an insulating substrate including a first surface; and

a wiring conductor located at the insulating substrate,

wherein the insulating substrate contains multiple bulk crystallites of SiC with different polytypes,

wherein the insulating substrate has a resistivity of 1×10 5 Ω·cm or more, and

wherein the insulating substrate has a vanadium content of 1×10 15 atoms/cm 3 or more and 1×10 18 atoms/cm 3 or less.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2022
From: ITOU, SEIICHIROU; ISHIZAKI, YUICHIRO; UMEKI, HARUKI
To: KYOCERA CORPORATION
Reel/Frame 059674/0141 →
Priority Claims (2)
JP 2019-198472 · Oct 31, 2019 · national
JP 2020-059294 · Mar 30, 2020 · national
Continuity (1)
Related Publication 20220367183A1 · Nov 17, 2022
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