Package substrate
A package substrate according to an embodiment includes an insulating layer; a first outer circuit pattern disposed on an upper surface of the insulating layer; a second outer circuit pattern disposed under a lower surface of the insulating layer; a first connection portion disposed on an upper surface of a first-first circuit pattern of the first outer circuit pattern; a first contact portion disposed on the first connection portion; a first device disposed on the first connection portion through the first contact portion; a second contact portion disposed under a lower surface of a second-first circuit pattern of the second outer circuit pattern; a second device attached to the second-first circuit pattern through the second contact portion; and a second connection portion disposed under a lower surface of a second-second circuit pattern of the second outer circuit pattern; wherein the first connection portion is disposed with a first width and a first interval, and wherein the second connection portion is disposed with a second width greater than the first width and a second interval greater than the first interval.
1 . A circuit board comprising:
an insulating structure including a plurality of insulating layers stacked along a vertical direction;
a connection part disposed under the insulating structure;
a first semiconductor device disposed under the connection part;
a first bump layer disposed under the insulating structure and spaced apart from the connection part and the first semiconductor device along a horizontal direction;
a second bump layer disposed under the insulating structure and spaced apart from the connection part, the first semiconductor device, and the first bump laver,
wherein the first bump layer overlaps the connection part and the first semiconductor device along the horizontal direction, and
wherein a width of the first bump layer in the horizontal direction and a width of the second bump layer in the horizontal direction are different from each other.
2 . The circuit board of claim 1 , wherein the first bump layer is positioned closer to an outer surface of the insulating structure than the connection part and the first semiconductor device.
3 . The circuit board of claim 1 , wherein a lower surface of the first bump layer and a lower surface of the first semiconductor device have different heights.
4 . The circuit board of claim 3 , wherein the lower surface of the first bump layer is positioned lower than the lower surface of the first semiconductor device based on a lower surface of the insulating structure.
5 . A circuit board comprising:
an insulating structure including a plurality of insulating layers stacked along a vertical direction;
a connection part disposed under the insulating structure;
a first semiconductor device disposed under the connection part;
a first bump layer disposed under the insulating structure and spaced apart from the connection part and the first semiconductor device along a horizontal direction;
a second bump layer disposed under the insulating structure and spaced apart from the connection part, the first semiconductor device, and the first bump layer; and
a second semiconductor device embedded in the insulating structure;
wherein the second bump layer overlaps the second semiconductor device along the vertical direction.
6 . The circuit board of claim 5 , wherein the second bump layer is located further from an outer surface of the insulating structure than the connection part, the first semiconductor device, and the first bump layer.
7 . The circuit board of claim 5 , wherein the second bump layer overlaps the first bump layer, the connection part, and the first semiconductor device along the horizontal direction.
8 . The circuit board of claim 5 , wherein the connection part and the first semiconductor device are disposed between the first bump layer and the second bump layer.
9 . The circuit board of claim 5 , wherein a width of the first bump layer in the horizontal direction and a width of the second bump layer in the horizontal direction are different from each other.
10 . The circuit board of claim 9 , wherein the width of the first bump layer in the horizontal direction is larger than the width of the second bump layer in the horizontal direction.
11 . The circuit board of claim 1 , further comprising:
a second semiconductor device embedded in the insulating structure.
12 . The circuit board of claim 11 , wherein the second bump layer overlaps the second semiconductor device along the vertical direction.
13 . The circuit board of claim 5 , further comprising:
a lower embedding insulation layer disposed under the insulating structure and embeds side portions of the first semiconductor device, the connection part, the first bump layer, and the second bump layer.
14 . A circuit board comprising:
an insulating structure including a plurality of insulating lavers stacked along a vertical direction;
a connection part disposed under the insulating structure;
a first semiconductor device disposed under the connection part;
a first bump layer disposed under the insulating structure and spaced apart from the connection part and the first semiconductor device along a horizontal direction;
an upper embedding insulation layer disposed on the insulating structure and having a cavity; and
a third semiconductor device disposed in the cavity,
wherein the first bump layer overlaps the connection part and the first semiconductor device along the horizontal direction.
15 . The circuit board of claim 14 , wherein a bottom surface of the cavity is positioned higher than an upper surface of the insulating structure.
16 . The circuit board of claim 14 , wherein a bottom surface of the cavity is inclined with respect to an upper surface of the insulating structure.
17 . The circuit board of claim 14 , wherein a height of the bottom surface of the cavity increases toward an inner wall of the cavity based on an upper surface of the structure.
18 . The circuit board of claim 14 , further comprising:
an upper wiring part disposed on the insulating structure, and
wherein a bottom surface of the cavity is positioned between an upper surface of the upper wiring part and a lower surface of the upper wiring part.