Integrated assemblies and methods of forming integrated assemblies
Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and said other region, and separates a first memory-block-region from a second memory-block-region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. Rings laterally surround lower regions of the conductive posts. The rings are between the conductive posts and the doped-semiconductor-material. The rings include laminates of two or more materials, with at least one of said two or more materials being insulative. Some embodiments include methods for forming integrated assemblies.
1 . A method of forming an integrated assembly, comprising:
forming a construction to include a first memory region, a second memory region laterally offset from the first memory region, and an intermediate region laterally between the first and second memory regions; the construction including a first stack extending across the first memory region, the second memory region and the intermediate region; the first stack comprising a metal-containing material, and alternating semiconductor-material-containing regions and intervening regions over the metal-containing material; there being at least three of the semiconductor-material-containing regions, with one of the semiconductor-material-containing regions being a central semiconductor-material-containing region and being vertically between two others of the semiconductor-material-containing regions;
forming rings to extend through the first stack; islands of the first stack being encircled by the rings, with said islands including lower conductive structures comprising the metal-containing material; the rings comprising laminates of two or more materials, with at least one of said two or more materials being insulative;
forming a second stack over the first stack and the rings; the second stack comprising alternating first and second levels, with the first levels comprising sacrificial material and the second levels comprising insulative material;
forming pillars extending through the second stack of the first and second memory regions and at least partially into the first stack of the first and second memory regions, the pillars including cell materials and channel material;
forming conductive posts extending through the second stack of the intermediate region and into the islands, said conductive posts being electrically coupled with the lower structures of the islands;
forming a slit-opening to pass through the second stack and to the central semiconductor-material-containing region of the first stack; the slit-opening extending across the first memory region, the intermediate region and the second memory region;
removing the central semiconductor-material-containing region from within the first memory region, the intermediate region and the second memory region with one or more etchants flowed into the slit-opening, at least one of the materials of the rings being resistant to said one or more etchants; the removing of the central semiconductor-material-containing region forming conduits in the first stacks within the first and second memory regions;
extending the conduits through the cell materials and to the channel material of the pillars;
forming doped-semiconductor-material within the extended conduits;
out-diffusing dopant from the doped-semiconductor-material into the channel material, the out-diffused dopant extending upwardly to at least one of the first levels; and
replacing at least some of the sacrificial material of the first levels with conductive material.
2 . The method of claim 1 further comprising forming a source-select-device to comprise said at least one of the first levels.
3 . The method of claim 1 wherein said at least one material of the rings comprises metal.
4 . The method of claim 1 wherein said at least one material of the rings comprises metal nitride.
5 . The method of claim 1 wherein said at least one material of the rings comprises carbon-doped silicon oxide.
6 . The method of claim 1 wherein said at least one material of the rings comprises carbon-doped silicon nitride.
7 . The method of claim 1 wherein said at least one material of the rings comprises SiON, where the chemical formula indicates primary constituents rather than a specific stoichiometry.
8 . The method of claim 1 wherein said at least one material of the rings consists of silicon.
9 . The method of claim 1 wherein said at least one material of the rings consists of carbon.
10 . The method of claim 1 wherein the metal-containing material is elevationally the lowest material of the first stack.
11 . The method of claim 1 wherein the central semiconductor-material-containing region comprises undoped semiconductor material.
12 . The method of claim 1 wherein the rings comprise at least three laminates of material.
13 . The method of claim 12 wherein two of the at least three laminates of material comprise the same composition.
14 . The method of claim 12 wherein one of the at least three laminates is between two laminates of material, the one laminate comprises a different composition than the two laminates of material.
15 . The method of claim 1 wherein the replacing of the at least some of the sacrificial material of the first levels is performed after the forming of the pillars.
16 . The method of claim 1 wherein the replacing of the at least some of the sacrificial material of the first levels is performed after the forming of the conductive posts.
17 . The method of claim 1 wherein the replacing of the at least some of the sacrificial material of the first levels is performed after at least one of the following method steps:
the forming of the slit-opening;
the removing of the central semiconductor-material-containing region;
the extending of the conduits;
the forming of the doped-semiconductor-material; and
the out-diffusing of the dopant.
18 . A method of forming an integrated assembly, comprising:
forming a construction to include a first memory region, a second memory region laterally offset from the first memory region, and an intermediate region laterally between the first and second memory regions; the construction including a first stack extending across the first memory region, the second memory region and the intermediate region; the first stack comprising alternating levels of semiconductor materials;
forming rings to extend through, and surround portions of, the first stack of the intermediate region;
forming pillars extending through at least partially into the first stack of the first and second memory regions, the pillars comprising cell materials and channel material;
forming conductive posts extending through at least partially into the first stack of the intermediate region;
removing at least one of the alternating levels of semiconductor materials to form conduits in the first stack within the first memory region, the second memory region and through the cell materials to the channel material of the pillars, at least one of the materials of the rings being resistant to one or more etchants utilized in the removing;
forming doped-semiconductor-material within the conduits; and
out-diffusing dopant from the doped-semiconductor-material into the channel material; and
after performing the forming of the pillars, forming a second stack over the first stack and the rings; the second stack comprising alternating levels of insulative material and conductive material.
19 . The method of claim 18 wherein the removing of at least one of the alternating levels of semiconductor materials comprises removing a level of undoped semiconductor material.
20 . The method of claim 19 wherein the level of undoped semiconductor material is between two levels of doped semiconductor material.
21 . A method of forming an integrated assembly, comprising:
forming a construction to include a first memory region, a second memory region laterally offset from the first memory region, and an intermediate region laterally between the first and second memory regions; the construction including a first stack extending across the first memory region, the second memory region and the intermediate region; the first stack comprising alternating levels of semiconductor material;
forming openings to extend through, and surround portions of, the first stack of the intermediate region;
a forming a first ring in the openings to surround the portions of the first stack;
forming a second ring surrounding the first ring;
forming a third ring surrounding the second ring;
forming pillars extending through at least partially into the first stack of the first and second memory regions, the pillars comprising cell materials and channel material;
forming conductive posts extending through at least partially into the first stack of the intermediate region;
removing at least one level of the semiconductor material to form conduits in the first stack within the first memory region, the second memory region and through the cell materials to the channel material of the pillars; at least one of the first, second and third rings being resistant to one or more etchants utilized in the removing;
forming doped-semiconductor-material within the conduits; and
out-diffusing dopant from the doped-semiconductor-material into the channel material; and
forming a second stack over the first stack and the first, second and third rings; the second stack comprising alternating levels of insulative material and conductive material.
22 . The method of claim 21 wherein the at least one of the first, second and third rings being resistant to one or more etchants comprises the second ring.