Profile control of isolation structures in semiconductor devices
A semiconductor device with doped shallow trench isolation (STI) structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure with first and second nanostructured layers arranged in an alternating configuration on the fin structure, depositing an oxide liner surrounding the superlattice structure and the fin structure in a first deposition process, forming a dopant source liner on the oxide liner, depositing an oxide fill layer on the dopant source liner in a second deposition process different from the first deposition process, performing a doping process to form a doped oxide liner and a doped oxide fill layer, removing portions of the doped oxide liner, the doped oxide fill layer, and the dopant source liner from sidewalls of the superlattice structure, and forming a gate structure on the fin structure and surrounding the first nanostructured layers.
1 . A method, comprising:
forming a fin base structure on a substrate;
forming a superlattice structure with first and second nanostructured layers arranged in an alternating configuration on the fin base structure;
depositing an oxide liner in contact with sidewalls of the first and second nanostructured layers and surrounding the superlattice structure and the fin base structure in a first deposition process;
forming a dopant source liner on the oxide liner;
depositing an oxide fill layer on the dopant source liner in a second deposition process different from the first deposition process;
performing a doping process to form a doped oxide liner and a doped oxide fill layer;
removing top portions of the doped oxide liner, the doped oxide fill layer, and the dopant source liner from sidewalls of the superlattice structure, while bottom portions of the doped oxide liner, the doped oxide fill layer, and the dopant source liner remain surrounding the fin base structure;
forming an isolation structure on the bottom portions of the doped oxide fill layer; and
forming a gate structure surrounding the first nanostructured layers.
2 . The method of claim 1 , wherein forming the dopant source liner comprises performing a nitridation process on the oxide liner.
3 . The method of claim 1 , wherein forming the dopant source liner comprises converting a top portion of the oxide liner into a nitride liner.
4 . The method of claim 1 , wherein performing the doping process comprises performing an anneal process on the oxide liner, the dopant source liner, and the oxide fill layer.
5 . The method of claim 1 , wherein performing the doping process comprises implanting the oxide liner with a first dopant concentration and implanting the oxide fill layer with a second dopant concentration that is greater than the first dopant concentration.
6 . The method of claim 1 , wherein performing the doping process comprises implanting the oxide liner and the oxide fill layer with nitrogen atoms from the dopant source liner.
7 . The method of claim 1 , wherein performing the doping process comprises increasing concentrations of nitrogen atoms in the oxide liner and the oxide fill layer and decreasing a concentration of nitrogen atoms in the dopant source liner.
8 . The method of claim 1 , further comprising forming a cladding layer on the sidewalls of the superlattice structure after removing the top portions of the doped oxide liner, the doped oxide fill layer, and the dopant source liner from the sidewalls of the superlattice structure.
9 . The method of claim 1 , wherein forming the isolation structure on the doped oxide fill layer comprises depositing an insulating layer on the doped oxide fill layer.
10 . The method of claim 1 , further comprising replacing a portion of the superlattice structure with a source/drain region.
11 . The method of claim 1 , wherein forming the gate structure comprises removing the second nanostructured layers.
12 . A method, comprising:
forming a superlattice structure with first and second semiconductor nanostructured layers arranged in an alternating configuration on a substrate;
forming a dopant source liner on the superlattice structure in a first deposition process;
forming, on the dopant source liner, a doped fill layer with a peak nitrogen concentration at an interface between the doped fill layer and the dopant source liner in a second deposition process different from the first deposition process;
removing portions of the dopant source liner and the doped fill layer from sidewalls of the superlattice structure; and
forming a gate structure surrounding the first semiconductor nanostructured layers.
13 . The method of claim 12 , wherein forming the doped fill layer comprises:
depositing an undoped oxide fill layer on the dopant source liner in a flowable deposition process; and
performing an anneal process on the undoped oxide fill layer and the dopant source liner.
14 . The method of claim 12 , wherein forming the doped fill layer comprises:
depositing an oxide fill layer on the dopant source liner in a flowable deposition process; and
implanting nitrogen atoms from the dopant source liner into the oxide fill layer.
15 . A method, comprising:
forming a semiconductor nanostructured layer on a substrate;
depositing, on and in contact with a top surface and sidewalls of the semiconductor nanostructured layer and the substrate, a first liner comprising a first material;
converting, using a nitridation process, a portion of the first liner into a second liner comprising a second material different from the first material;
depositing a dielectric layer on the second liner;
doping the dielectric layer with nitrogen dopants to form a doped dielectric layer with a peak nitrogen concentration at an interface between the doped dielectric layer and the second liner; and
forming a gate structure surrounding the semiconductor nanostructured layer.
16 . The method of claim 15 , wherein converting the portion of the first liner into the second liner comprises converting the portion of the first liner into a silicon nitride liner.
17 . The method of claim 15 , wherein converting the portion of the first liner into the second liner comprises exposing the first liner to ammonia gas.
18 . The method of claim 15 , further comprising doping the first liner with the nitrogen dopants.
19 . The method of claim 15 , further comprising converting the first liner to a doped first liner.
20 . The method of claim 15 , further comprising forming a barrier layer on the doped dielectric layer prior to forming the gate structure.