IP Library Granted Patent US 12,538,852
Granted Patent B2
US 12,538,852 · App. 18/624,686 · Granted Jan 27, 2026

Package structure containing chip structure with inclined sidewalls

Inventors: Shu-Shen Yeh (Taoyuan, TW); Po-Chen Lai (Hsinchu County, TW); Che-Chia Yang (Taipei, TW); Li-Ling Liao (Hsinchu, TW); Po-Yao Lin (Zhudong Township, Hsinchu County, TW); Shin-Puu Jeng (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L25/0655H01L21/4857H01L21/563H01L21/78H01L23/3185H01L23/49822
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Quick Facts
Patent No.
US 12,538,852
App. No.
18/624,686
Granted
Jan 27, 2026
Kind
B2
Abstract

A package structure is provided. The package structure includes a chip structure having opposite surfaces with different widths. The chip structure has an inclined sidewall between the opposite surfaces. The package structure also includes a protective layer laterally surrounding the chip structure.

Claims (34)

1 . A package structure, comprising:

a chip structure having opposite surfaces with different widths, wherein the chip structure has an inclined sidewall between the opposite surfaces, the chip structure has a first side region, a second side region, and a corner region, the first side region and the second side region meet at the corner region, the chip structure has a first inclined sidewall in the first side region, the chip structure has a second inclined sidewall in the corner region, and the first inclined sidewall is steeper than the second inclined sidewall, wherein in a top view, the corner region has a rounded profile, the first side region has a first substantially straight-line profile and extends towards the corner region along a first direction, the second side region has a second substantially straight-line profile and extends towards the corner region along a second direction, and the second direction is perpendicular to the first direction; and

a protective layer laterally surrounding the chip structure.

2 . The package structure as claimed in claim 1 , further comprising:

a second chip structure below the chip structure, wherein the second chip structure has inclined sidewalls.

3 . The package structure as claimed in claim 2 , further comprising:

a third chip structure laterally spaced apart from the chip structure, wherein the protective layer laterally surrounds the third chip structure.

4 . The package structure as claimed in claim 3 , wherein the third chip structure has inclined sidewalls.

5 . The package structure as claimed in claim 4 , wherein the second chip structure extends across a portion of the chip structure and a portion of the third chip structure.

6 . The package structure as claimed in claim 2 , further comprising:

a redistribution structure between the chip structure and the second chip structure, wherein conductive features of the redistribution structure comprise a plurality of conductive vias, and each of the conductive vias shrinks along a direction towards the chip structure.

7 . The package structure as claimed in claim 1 , wherein the chip structure further has a vertical sidewall connecting a bottom edge of the inclined sidewall.

8 . A package structure, comprising:

a chip structure over a redistribution structure, wherein the chip structure has an inclined sidewall, the inclined sidewall is at an acute angle to a vertical, the vertical is a direction perpendicular to a main surface of the chip structure, and the acute angle is in a range from about 12 degrees to about 45 degrees, wherein the chip structure has a first side region, a second side region, and a corner region, the first side region and the second side region meet at the corner region, the chip structure has a first inclined sidewall in the first side region, the chip structure has a second inclined sidewall in the corner region, and the first inclined sidewall is steeper than the second inclined sidewall, wherein in a top view, the corner region has a rounded profile, the first side region has a first substantially straight-line profile and extends towards the corner region along a first direction, the second side region has a second substantially straight-line profile and extends towards the corner region along a second direction, and the second direction is perpendicular to the first direction; and

a protective layer over the redistribution structure, wherein the protective layer surrounds the chip structure.

9 . The package structure as claimed in claim 8 , wherein in the top view, the chip structure has a second corner region, a third corner region, and a fourth corner region, and the second corner region, the third corner region, and the fourth corner region have rounded profiles.

10 . The package structure as claimed in claim 8 , wherein the protective layer is in direct contact with the inclined sidewall of the chip structure.

11 . The package structure as claimed in claim 8 , wherein the chip structure further has a vertical sidewall connecting a bottom edge of the inclined sidewall.

12 . The package structure as claimed in claim 8 , further comprising a second chip structure over the redistribution structure and surrounded by the protective layer, wherein the second chip structure is wider than the chip structure, the second chip structure has a second inclined sidewall, the second inclined sidewall is at a second acute angle to the vertical, and the second acute angle of the second chip structure is greater than the acute angle of the chip structure.

13 . A package structure, comprising:

a chip structure over a redistribution structure, wherein the chip structure has a front side and a back side opposite to the front side, and the front side and the bottom side have different widths, wherein the chip structure has a first side region, a second side region, and a corner region, the first side region and the second side region meet at the corner region, the chip structure has a first inclined sidewall in the first side region, the chip structure has a second inclined sidewall in the corner region, and the first inclined sidewall is steeper than the second inclined sidewall, wherein in a top view, the corner region has a curved profile, the first side region has a first substantially straight-line profile and extends towards the corner region along a first direction, the second side region has a second substantially straight-line profile and extends towards the corner region along a second direction, and the second direction is perpendicular to the first direction; and

a protective layer over the redistribution structure, wherein the protective layer surrounds the chip structure.

14 . The package structure as claimed in claim 13 , wherein the chip structure has a sidewall connecting the front side and the back side, and the sidewall comprises at least one inclined portion.

15 . The package structure as claimed in claim 13 , wherein the sidewall is a curved sidewall.

16 . The package structure as claimed in claim 6 , further comprising:

a circuit substrate bonded to the redistribution structure, wherein the second chip structure is between the redistribution structure and the circuit substrate.

17 . The package structure as claimed in claim 16 , wherein a bottommost surface of the second chip structure is vertically between a topmost surface of the circuit substrate and a lower surface of the circuit substrate.

18 . The package structure as claimed in claim 13 , wherein the redistribution structure has a plurality of conductive features and a plurality of polymer-containing layers surrounding the conductive features, the conductive features of the redistribution structure comprise a plurality of conductive vias, and each of the conductive vias gradually shrinks along a direction towards the chip structure.

19 . The package structure as claimed in claim 13 , further comprising:

a circuit substrate bonded to the redistribution structure through a plurality of solder bumps;

a second chip structure bonded to the redistribution structure, wherein the circuit substrate laterally surrounds a lower portion of the second chip structure; and

an underfill material laterally surrounding the solder bumps and the second chip structure, wherein the circuit substrate laterally surrounds a lower portion of the underfill material.

20 . The package structure as claimed in claim 1 , further comprising:

a redistribution structure, wherein the chip structure and the protective layer are over the redistribution structure, the chip structure is in direct contact with a conductive feature of the redistribution structure, and the chip structure is in direct contact with an insulating layer of the redistribution structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 2, 2024
From: YEH, SHU-SHEN; LAI, PO-CHEN; YANG, CHE-CHIA; LIAO, LI-LING; LIN, PO-YAO; JENG, SHIN-PUU
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 066982/0058 →
Continuity (2)
Division 17459314 · Aug 27, 2021
Related Publication 20240250069A1 · Jul 25, 2024
References Cited (32)
US 8350381B2 · Theuss · 2013 [cited by examiner]
US 9000584B2 · Lin · 2015 [cited by applicant]
US 9048222B2 · Hung · 2015 [cited by applicant]
US 9048233B2 · Wu · 2015 [cited by applicant]
US 9064879B2 · Hung · 2015 [cited by applicant]
US 9111949B2 · Yu · 2015 [cited by applicant]
US 9263511B2 · Yu · 2016 [cited by applicant]
US 9281254B2 · Yu · 2016 [cited by applicant]
US 9368460B2 · Yu · 2016 [cited by applicant]
US 9372206B2 · Wu · 2016 [cited by applicant]
US 9496189B2 · Yu · 2016 [cited by applicant]
US 10770405B2 · Huang · 2020 [cited by applicant]
US 11024616B2 · Chen · 2021 [cited by examiner]
US 11309271B2 · Lai · 2022 [cited by applicant]
US 11521938B2 · Cheng · 2022 [cited by examiner]
US 20020042161A1 · Sato · 2002 [cited by examiner]
US 20030162369A1 · Kobayashi · 2003 [cited by examiner]
US 20080006900A1 · Chan · 2008 [cited by examiner]
US 20080157342A1 · Yang · 2008 [cited by examiner]
US 20080197435A1 · Yang · 2008 [cited by examiner]
US 20110175225A1 · Seddon · 2011 [cited by examiner]
US 20160099195A1 · Huang · 2016 [cited by applicant]
US 20170103957A1 · Li · 2017 [cited by examiner]
US 20200035604A1 · Rubin · 2020 [cited by examiner]
US 20200044099A1 · Chang · 2020 [cited by examiner]
US 20210098421A1 · Wu · 2021 [cited by examiner]
US 20210111114A1 · Lee · 2021 [cited by examiner]
US 20220181225A1 · Chen · 2022 [cited by examiner]
US 20220310467A1 · Tseng · 2022 [cited by examiner]
TW 201903996A · 2019 [cited by applicant]
TW 202105658A · 2021 [cited by applicant]
Chinese language office action dated Dec. 12, 2022, issued in application No. TW 111110333. [cited by applicant]