IP Library › Granted Patent US 12,543,517
Granted Patent B2
US 12,543,517 · App. 18/314,885 · Granted Feb 3, 2026

System and method for semiconductor structure

Inventors: David Eitan Barlaz (Albany, NY); Angelique Raley (Albany, NY)
Assignee: TOKYO ELECTRON LIMITED
H01L21/02636H01J37/32339H01J37/32715H01L21/268H01L21/3065
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Quick Facts
Patent No.
US 12,543,517
App. No.
18/314,885
Granted
Feb 3, 2026
Kind
B2
Abstract

A method includes forming a first masking layer over a substrate, the first masking layer including a first mask line and a second mask line, heating respective top surfaces of the first mask line and the second mask line with polarized light, and forming a second masking layer over the first masking layer with an area selective deposition process. The second masking layer is thinner over a sidewall of the first mask line than over a top surface of the first mask line.

Claims (34)

1 . A method for an area selective deposition process, the method comprising:

forming a first masking layer over a substrate, the first masking layer comprising a first mask line and a second mask line, wherein a trench between the first mask line and the second mask line has a first width;

in a plasma processing chamber, heating respective top surfaces of the first mask line and the second mask line with polarized light, wherein the first width is smaller than half a wavelength of the polarized light; and

in the plasma processing chamber, forming a second masking layer over the first masking layer with an area selective deposition process, wherein the second masking layer is thinner over a sidewall of the first mask line than over a top surface of the first mask line.

2 . The method of claim 1 , wherein the polarized light is linearly polarized.

3 . The method of claim 1 , wherein the polarized light is circularly polarized.

4 . The method of claim 1 , wherein the polarized light enters the plasma processing chamber through a top surface of the plasma processing chamber.

5 . The method of claim 1 , wherein the polarized light enters the plasma processing chamber through a sidewall of the plasma processing chamber.

6 . The method of claim 1 , wherein the polarized light is projected into the plasma processing chamber by a digital light projection system.

7 . The method of claim 1 , wherein a temperature of the respective top surfaces of the first mask line and the second mask line is higher than a temperature of a bottom surface of the trench after heating the respective top surfaces of the first mask line and the second mask line with polarized light.

8 . A method for manufacturing a semiconductor structure, the method comprising:

placing a substrate into a plasma processing chamber, a patterned first masking layer being over a target layer of the substrate;

bombarding the patterned first masking layer with linearly polarized light, wherein a polarization direction of the linearly polarized light is aligned with a pattern of trenches through the patterned first masking layer;

performing a first area selective deposition of a second masking layer over the patterned first masking layer;

patterning the target layer using the second masking layer and the patterned first masking layer as an etching mask; and

forming a pattern between remaining portions of the target layer.

9 . The method of claim 8 , further comprising, partially through an etch process to pattern the target layer, bombarding the substrate with linearly polarized light and performing a second area selective deposition of the second masking layer.

10 . The method of claim 8 , wherein the first area selective deposition forms a greater proportion of material over top surfaces of the patterned first masking layer than over sidewalls of the patterned first masking layer.

11 . The method of claim 8 , wherein the plasma processing chamber is part of an inductively coupled plasma processing system.

12 . The method of claim 8 , wherein the plasma processing chamber is part of a capacitively coupled plasma processing system.

13 . The method of claim 8 , wherein the linearly polarized light is produced by a pulsed laser generator.

14 . A method for manufacturing a semiconductor structure, the method comprising:

forming a first masking layer over a target layer, the target layer being over a substrate, the first masking layer comprising a first mask line and a second mask line, wherein a trench between the first mask line and the second mask line has a first width;

placing the substrate into a plasma processing chamber;

heating respective top surfaces of the first mask line and the second mask line with polarized light, the first width being smaller than half a wavelength of the polarized light;

performing a first area selective deposition of a second masking layer over the first masking layer;

patterning the target layer using the second masking layer and the first masking layer as an etching mask; and

forming a pattern between remaining portions of the target layer.

15 . The method of claim 14 , wherein the polarized light is linearly polarized.

16 . The method of claim 15 , wherein a polarization direction of the polarized light is aligned with the trench.

17 . The method of claim 14 , wherein the polarized light is circularly polarized.

18 . The method of claim 14 , wherein the second masking layer is thinner over a sidewall of the first mask line than over a top surface of the first mask line.

19 . The method of claim 14 , wherein the polarized light enters the plasma processing chamber through a top surface of the plasma processing chamber.

20 . The method of claim 14 , wherein the polarized light enters the plasma processing chamber through a sidewall of the plasma processing chamber.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 10, 2023
From: BARLAZ, DAVID EITAN; RALEY, ANGELIQUE
To: TOKYO ELECTRON LIMITED
Reel/Frame 063591/0614 →
Continuity (1)
Related Publication 20240379354A1 · Nov 14, 2024
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