Forming liners to facilitate the formation of copper-containing vias in advanced technology nodes
A semiconductor device includes a source/drain component of a transistor. A source/drain contact is disposed over the source/drain component. A source/drain via is disposed over the source/drain contact. The source/drain via contains copper. A first liner at least partially surrounds the source/drain via. A second liner at least partially surrounds the first liner. The first liner and the second liner are disposed between the source/drain contact and the source/drain via. The first liner and the second liner have different material compositions.
1 . A semiconductor device, comprising:
a source/drain component of a transistor;
a gate structure of the transistor disposed adjacent to the source/drain component, wherein the gate structure includes both a gate dielectric and a gate electrode;
a source/drain contact disposed over the source/drain component, wherein an uppermost surface of the source contact has a greater vertical elevation than an uppermost surface of the gate structure;
a silicide layer disposed on a bottom surface and side surfaces of the source/drain contact in a cross-sectional side view;
a source/drain via disposed over the source/drain contact, wherein the source/drain via contains copper;
a first liner that at least partially surrounds the source/drain via;
a second liner that at least partially surrounds the first liner, wherein the first liner and the second liner are disposed between the source/drain contact and the source/drain via, and wherein the first liner and the second liner have different material compositions; and
a dielectric component disposed adjacent to the source/drain contact and over the source/drain component, wherein the silicide layer is disposed between the dielectric component and the source/drain contact, wherein a maximum vertical dimension of the dielectric component is substantially similar to a maximum vertical dimension of the silicide layer, and wherein a bottom surface of the dielectric component is disposed closer to an upper surface of the source/drain component than a bottom surface of the source/drain contact.
2 . The semiconductor device of claim 1 , further comprising: an etching-stop layer (ESL) disposed over the source/drain contact; and
an interlayer dielectric (ILD) disposed over the ESL, wherein a side surface of the second liner extends to both the ESL and the ILD.
3 . The semiconductor device of claim 1 , wherein:
the first liner extends to the source/drain via;
the second liner extends to the source/drain contact;
the source/drain via further contains manganese;
the first liner contains ruthenium, cobalt, or tungsten; and
the second liner contains tantalum nitride or titanium nitride.
4 . The semiconductor device of claim 1 , further comprising a gate spacer disposed on a side surface of the gate structure, wherein a top surface of the dielectric component is located higher than a top surface of the gate spacer.
5 . The semiconductor device of claim 1 , wherein:
the first liner has a first thickness in a range between about 10 angstroms and about 15 angstroms; and
the second liner has a second thickness in a range between about 10 angstroms and about 20 angstroms.
6 . The semiconductor device of claim 1 , wherein the gate structure includes both a gate dielectric and a gate electrode, and wherein the semiconductor device further includes:
a gate via disposed over the gate electrode, wherein the gate via contains copper;
a third liner that at least partially surrounds the gate via; and
a fourth liner that at least partially surrounds the third liner, wherein the third liner and the fourth liner are disposed between the gate structure and the gate via, and wherein the third liner and the fourth liner have different material compositions.
7 . The semiconductor device of claim 6 , wherein:
the third liner and the first liner have same material compositions; and
the fourth liner and the second liner have same material compositions.
8 . The semiconductor device of claim 6 , further comprising a capping layer disposed between the gate structure and the gate via, wherein the capping layer contains tungsten, and wherein the capping layer is wider than the gate structure and has a substantially flat bottom surface in a cross-sectional side view.
9 . A semiconductor device, comprising:
a gate structure of a transistor;
gate spacers disposed on side surfaces of the gate structure;
a gate via disposed over an upper surface of the gate structure, wherein the gate via contains copper and manganese, and wherein a bottom surface and side surfaces of the gate via are surrounded by one or more liner layers; and
a capping layer disposed between the gate structure and the gate via, wherein a material composition of the capping layer is configured such that the capping layer prevents a penetration of the copper or the manganese of the gate via into the gate structure, wherein a lateral dimension of the capping layer exceeds a maximum lateral dimension of the gate structure in a cross-sectional side view, and wherein a first portion of the capping layer located directly over the gate spacers and a second portion of the capping layer located directly over the gate structure have substantially co-planar bottom surfaces.
10 . The semiconductor device of claim 9 , wherein the gate structure includes both a gate dielectric and a gate electrode, and wherein the capping layer contains fluorine-free tungsten.
11 . The semiconductor device of claim 9 , wherein:
the one or more liner layers include a first liner layer and a second liner layer having a different material composition than the first liner layer;
an inside surface of the first liner layer is in direct contact with the bottom surface and the side surfaces of the gate via;
an inside surface of the second liner layer is in direct contact with an outside surface of the first liner layer; and
an outside surface of the second liner layer is in direct contact with an upper surface of the capping layer.
12 . The semiconductor device of claim 11 , wherein:
the first liner layer contains ruthenium, cobalt, or tungsten;
the first liner layer has a first thickness in a range between about 10 angstroms and about 15 angstroms;
the second liner layer contains tantalum nitride or titanium nitride; and
the second liner layer has a second thickness in a range between about 10 angstroms and about 20 angstroms.
13 . The semiconductor device of claim 9 , wherein the one or more liner layers include one or more gate via liner layers, and wherein the semiconductor device further comprises:
a source/drain component of the transistor disposed adjacent to the gate structure;
a source/drain contact disposed over the source/drain component; and
a source/drain via disposed over the source/drain contact, wherein the source/drain via contains copper and manganese, wherein a bottom surface and side surfaces of the source/drain via are surrounded by one or more source/drain via liner layers.
14 . The semiconductor device of claim 13 , wherein the one or more gate via liner layers contain similar materials as the one or more source/drain via liner layers.
15 . A semiconductor device, comprising:
an epi-layer;
a conductive contact formed over the epi-layer;
a conductive via formed over the conductive contact;
a first liner that at least partially surrounds, and is in direct contact with, the conductive via, wherein the first liner has a first material composition;
a second liner that at least partially surrounds the first liner, wherein the second liner is in direct contact with the conductive contact, and wherein the second liner has a second material composition different from the first material composition;
a silicide layer that surrounds a bottom surface and side surfaces of the conductive contact in a cross-sectional side view; and
a dielectric layer disposed over the epi-layer, wherein the silicide layer is disposed between the dielectric layer and the conductive contact, wherein the dielectric layer has a substantially similar vertical dimension as a combination of the silicide layer and the conductive contact.
16 . The semiconductor device of claim 15 , wherein the first liner and the second liner are disposed laterally between the conductive contact and the conductive via in the cross-sectional side view.
17 . The semiconductor device of claim 15 , wherein:
the conductive via contains copper and manganese;
the first material composition includes ruthenium, cobalt, or tungsten; and
the second material composition includes tantalum nitride or titanium nitride.
18 . The semiconductor device of claim 15 , further comprising a gate structure formed adjacent to the epi-layer in the cross-sectional side view, wherein a top surface of the silicide layer is located higher than a top surface of the gate structure.
19 . The semiconductor device of claim 15 , wherein the epi-layer is a source/drain component of a transistor, and wherein the semiconductor device further includes:
a gate structure formed adjacent to the source/drain component in the cross-sectional side view;
a gate via formed over the gate structure in the cross-sectional side view, wherein the gate via contains copper;
a third liner that at least partially surrounds the gate via in the cross-sectional side view; and
a fourth liner that at least partially surrounds the third liner in the cross-sectional side view, wherein the third liner and the fourth liner are disposed between the gate structure and the gate via in the cross-sectional side view, wherein the third liner has the first material composition, and wherein the fourth liner has the second material composition.
20 . The semiconductor device of claim 19 , wherein the gate structure includes both a gate dielectric and a gate electrode, and wherein the semiconductor device further comprises a capping layer formed between the gate structure and the gate via in the cross-sectional side view, wherein the capping layer contains tungsten, and wherein the capping layer is wider than the gate structure in the cross-sectional side view.