IP Library Granted Patent US 12,557,557
Granted Patent B2
US 12,557,557 · App. 18/239,079 · Granted Feb 17, 2026

Method for fabricating magnetoresistive random access memory (MRAM) device

Inventors: Hui-Lin Wang (Taipei, TW); Tai-Cheng Hou (Tainan, TW); Wei-Xin Gao (Tainan, TW); Fu-Yu Tsai (Tainan, TW); Chin-Yang Hsieh (Tainan, TW); Chen-Yi Weng (New Taipei, TW); Jing-Yin Jhang (Tainan, TW); Bin-Siang Tsai (Changhua County, TW); Kun-Ju Li (Tainan, TW); Chih-Yueh Li (Taipei, TW); Chia-Lin Lu (Taoyuan, TW); Chun-Lung Chen (Tainan, TW); Kun-Yuan Liao (Hsinchu, TW); Yu-Tsung Lai (Tainan, TW); Wei-Hao Huang (New Taipei, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H10N50/10H01L21/762H01L21/76802H10N50/80H10N35/01
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Quick Facts
Patent No.
US 12,557,557
App. No.
18/239,079
Granted
Feb 17, 2026
Kind
B2
Abstract

A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

Claims (12)

1 . A method for fabricating semiconductor device, comprising:

forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate;

performing an atomic layer deposition (ALD) process to form a passivation layer on the first MTJ and the second MTJ and forming an opening between the first MTJ and the second MTJ;

performing an etching process to remove part of the passivation layer while the passivation layer remaining directly contacting a top surface of the first MTJ; and

forming an ultra low-k (ULK) dielectric layer on the passivation layer remaining directly on the top surface of the first MTJ.

2 . The method of claim 1 , further comprising:

performing the etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ.

3 . The method of claim 2 , further comprising performing the etching process for expanding the opening.

4 . The method of claim 1 , wherein the passivation layer comprises a curve concave upward between the first MTJ and the second MTJ.

5 . The method of claim 1 , wherein the passivation layer comprises a curve concave downward directly on top of the first MTJ.

6 . The method of claim 1 , wherein the passivation layer comprises a curve concave downward directly on top of the second MTJ.

7 . The method of claim 1 , wherein the passivation layer comprises tetraethyl orthosilicate (TEOS), silicon oxide, or silicon nitride.

Priority Claims (1)
CN 201811612412.5 · Dec 27, 2018 · national
Continuity (4)
Continuation 17533003 · Nov 22, 2021
Continuation 17134460 · Dec 27, 2020
Division 16255754 · Jan 23, 2019
Related Publication 20230403946A1 · Dec 14, 2023
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