Backside power via
Embodiments of the present invention are directed to processing methods and resulting structures for providing power vias through a wafer backside. In a non-limiting embodiment of the invention, a gate and a source or drain (S/D) region are formed on a substrate. A bi-layer liner is formed in a gate cut of the gate. The bi-layer liner includes a first liner on sidewalls of the gate cut and a second liner between the first liner. A top portion of the second liner is replaced with a first portion of a backside power via and the semiconductor device is flipped. A bottom portion of the second liner is replaced with a second portion of the backside power via.
1 . A method for forming a semiconductor device, the method comprising:
forming a gate and a source or drain (S/D) region on a substrate;
forming a bi-layer liner in a gate cut of the gate, the bi-layer liner comprising a first liner on sidewalls of the gate cut and a second liner between the first liner;
replacing a top portion of the second liner with a first portion of a backside power via;
flipping the semiconductor device; and
replacing a bottom portion of the second liner with a second portion of the backside power via.
2 . The method of claim 1 , further comprising forming a backside power rail on the second portion of the backside power via.
3 . The method of claim 2 , further comprising recessing the substrate.
4 . The method of claim 3 , further comprising forming a dielectric cap on a recessed surface of the substrate, wherein the substrate is electrically isolated from the second portion of the backside power via and the backside power rail by the dielectric cap.
5 . The method of claim 1 , further comprising forming a S/D contact on the S/D region, the S/D contact in direct contact with the first portion of the backside power via.
6 . The method of claim 1 , wherein replacing the top portion of the second liner with the first portion of the backside power via comprises recessing the second liner.
7 . The method of claim 1 , wherein the first liner of the bi-layer liner comprises a first material and the second liner of the bi-layer liner comprises a second material that can be removed selective to the first material.
8 . A semiconductor device comprising:
a front end of line structure comprising a gate and a source or drain (S/D) region on a substrate, the front end of line structure further comprising a bi-layer liner in a gate cut of the gate, the bi-layer liner comprising a first liner on sidewalls of the gate cut and a second liner between the first liner, the second liner recessed from a bottommost surface of the first liner in a channel region of the gate cut and absent in the S/D region; and
a back end of line structure on a backside surface of the front end of line structure, the back end of line structure comprising a second portion of the backside power via, the second portion of the backside power via extending between the first liner to contact the recessed portion of the second liner in the channel region of the gate cut.
9 . The semiconductor device of claim 8 , further comprising a backside power rail on the second portion of the backside power via.
10 . The semiconductor device of claim 9 , wherein the substrate is recessed below a surface of the bi-layer liner.
11 . The semiconductor device of claim 10 , further comprising a dielectric cap on a recessed surface of the substrate, wherein the substrate is electrically isolated from the second portion of the backside power via and the backside power rail by the dielectric cap.
12 . The semiconductor device of claim 8 , further comprising a S/D contact on the S/D region, the S/D contact in direct contact with the first portion of the backside power via.
13 . The semiconductor device of claim 8 , wherein a portion of the second liner is in direct contact with the second portion of the backside power via.
14 . The semiconductor device of claim 8 , wherein the first liner of the bi-layer liner comprises a first material and the second liner of the bi-layer liner comprises a second material that can be removed selective to the first material.
15 . A semiconductor device comprising:
a front end of line structure comprising a gate and a source or drain (S/D) region over a first surface of a substrate, the front end of line structure further comprising a first liner on sidewalls of a gate cut and a second liner between the first liner, the second liner recessed from a bottommost surface of the first liner in a channel region of the gate cut and absent in the S/D region;
a first back end of line structure over the first surface of the substrate, the first back end of line structure comprising a S/D contact on the S/D region, the S/D contact in direct contact with the first portion of the backside power via; and
a second back end of line structure over a second surface of the substrate opposite the first surface of the substrate, the second back end of line structure comprising a second portion of the backside power via, the second portion of the backside power via extending between the first liner to contact the recessed portion of the second liner in the channel region of the gate cut.
16 . The semiconductor device of claim 15 , further comprising a backside power rail on the second portion of the backside power via.
17 . The semiconductor device of claim 16 , wherein the substrate is recessed below a surface of first liner.
18 . The semiconductor device of claim 17 , further comprising a dielectric cap on a recessed surface of the substrate, wherein the substrate is electrically isolated from the second portion of the backside power via and the backside power rail by the dielectric cap.
19 . The semiconductor device of claim 15 , wherein a portion of the second liner is in direct contact with the second portion of the backside power via.
20 . The semiconductor device of claim 15 , wherein the first liner comprises a first material and the second liner comprises a second material that can be removed selective to the first material.